As logic systems get larger and more complex, theirsupply current requirements continue to rise. Systemsrequiring 100A are fairly common. A high current powersupply to meet such requirements usually requires parallelingseveral power regulators to alleviate the thermalstress on the individual power components. A powersupply designer is left with the choice of how to drive theseparalleled regulators: brute-force single-phase or smartPolyPhaseTM.
上传时间： 2013-10-08
上传用户：zhqzal1014
Notebook and palmtop systems need a multiplicity ofregulated voltages developed from a single battery. Smallsize, light weight, and high efficiency are mandatory forcompetitive solutions in this area. Small increases inefficiency extend battery life, making the final productmuch more usable with no increase in weight. Additionally,high efficiency minimizes the heat sinks needed onthe power regulating components, further reducing systemweight and size.
上传时间： 2013-11-11
上传用户：大三三
为了改变目前电网现场作业管理的变电巡检、变电检修试验、输电线路巡检检修等管理系统各自独立运行，信息不能共享，功能、效率受限，建设和维护成本高的现状，提出了采用B/S+C/S构架模式，将各现场作业管理模块和生产MIS（管理系统）集成为一体的现场作业管理系统的设计方案，做到各子系统和生产MIS软硬资源共享，做到同一数据唯一入口、一处录入多处使用。各子系统设备人员等基础信息来源于生产管理系统，各子系统又是生产管理系统的作业数据、缺陷信息的重要来源。经过研究试用成功和推广应用，目前该系统已在江西电网220 kV及以上变电站全面应用。 Abstract: In order to improve the status that the substation field inspection system， substation equipments maintenance and testing system， power-line inspection and maintenance system are running independent with each other. They can?蒺t share the resource information which accordingly constrains their functions and efficiency， and their construction and maintenance costs are high. This paper introduces a field standardized work management system based on B/S+C/S mode， integrating all field work management systems based on MIS and share the equipments and employee?蒺s data of MIS，the field work data of the sub systems are the source information of MIS， by which the same single data resouce with one-time input can be utilized in multiple places. After the research and testing， this system is triumphantly using in all 220kV and above substations in Jiangxi grid.
上传时间： 2013-11-15
上传用户：han_zh
数字控制的交流调速系统所选用的微处理器、功率器件及产生PWM波的方法是影响交流调速系统性能好坏的直接因素。在介绍了正弦脉宽调制(SPWM)技术的基础上，设计了一种以8098单片机作为控制器，以智能功率模块IPM为开关器件的变频调速系统。通过软件编程，产生正弦脉冲宽度调制波形来控制绝缘栅双极晶体管的导通和关断，从而达到控制异步电动机转速的目的。实验结果表明，该系统可调频率调电压，稳定度高，调速范围宽，具有较强的实用价值 Abstract: AC variable speed with digital control systems used microprocessors， power devices and generate PWM wave is the direct factors of affecting the performance AC speed regulation system. On the basis of introducing the sinusoidal pulse width modulation (SPWM) technology，this paper designed variable speed system which used 8098 as a controller， intelligent power module IPM as switching device. Through software programming， resulting in sinusoidal pulse width modulation waveform to control the insulated gate bipolar transistor turn on and off， so as to achieve the purpose of speed control of induction motors. Experimental results show that the system can adjust frequency modulation voltage， high stability， wide speed range， has a strong practical value.
上传时间： 2013-11-14
上传用户：ynwbosss
介绍了当前普通标记机控制系统现状及其存在缺点，给出气动标记机及相频修正PWM模式的工作原理。采用ATmega16单片机和USB转换RS232接口器件CH341T实现驱动控制系统与PC的实时通讯，标记控制系统可升级到USB接口。采用基于ATmega16的相频修正PWM替换555振荡电路产生的PWM，可直接通过软件调整PWM信号。使用达林顿三极管TIP122替代直流继电器驱动高频电磁阀，使得电磁阀驱动电路简单，成本低廉。该控制系统已成功应用于气动标记机。 Abstract: In this paper,the actuality and demerit of the common gas marking machine control systems are described.The operation principle of the gas marking machine and the phase and frequency correct PWM of ATmega16is introduced.The real-time communication between the driving control system and PC by CH341T which its function is translated USB to RS232is realized,the control systems is updated grade to USB interface.The PWM signal can be adjustable by software for the555surge circuit was substituted by the phase and frequency.The high frequency electromagnetic value’s driving circuit by DC relay is replaced by TIP122,therefore,the circuit is become simple and the cost cheap.The control systems has been widely used in gas marking machine.
上传时间： 2013-10-17
上传用户：1427796291
以AVR单片机ATmega8和USB接口器件PDIUSBD12为核心，基于标准的USB1.1协议，设计一种通用USB接口模块，以满足嵌入式系统中对USB接口的需求。对模块的硬件电路或单片机固件程序的硬件接口层稍加修改即可用于其他各种微处理器。该模块可为各种嵌入式系统增加USB接口,实现与USB主机系统通信。 Abstract: Based on AVR microcontroller ATmega8 and USB interface chip PDIUSBD12, a general USB interface module is designed according to USB1.1 protocol for various requirements of embedded systems. Only with few modifications in circuit or hardware abstract layer of firmware, the module can be used on many types of microprocessors. All kinds of embedded systems can realize high speed and stable communication with USB host systems, owing to the facility of this module.
上传时间： 2014-01-08
上传用户：赵云兴
The TJA1042 is a high-speed CAN transceiver that provides an interface between aController Area Network (CAN) protocol controller and the physical two-wire CAN bus.The transceiver is designed for high-speed (up to 1 Mbit/s) CAN applications in theautomotive industry, providing the differential transmit and receive capability to (amicrocontroller with) a CAN protocol controller.
标签： High-speed transce 1042 TJA
上传时间： 2014-12-27
上传用户：气温达上千万的
The TJA1051 is a high-speed CAN transceiver that provides an interface between aController Area Network (CAN) protocol controller and the physical two-wire CAN bus.The transceiver is designed for high-speed (up to 1 Mbit/s) CAN applications in theautomotive industry, providing differential transmit and receive capability to (amicrocontroller with) a CAN protocol controller.
标签： High-speed transce 1051 TJA
上传时间： 2013-10-17
上传用户：jisujeke
中文版详情浏览：http://www.elecfans.com/emb/fpga/20130715324029.html Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications. The UltraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the UltraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation. Some of the UltraScale architecture breakthroughs include: • Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50% • Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability • Potential timing-closure problems and interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization • 3D IC integration makes it possible to build larger devices one process generation ahead of the current industr y standard • Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bandwidth is available within even smaller system power budgets • Greatly enhanced DSP and packet handling The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.
标签： UltraScale Xilinx 架构
上传时间： 2013-11-13
上传用户：瓦力瓦力hong
XAPP520将符合2.5V和3.3V I/O标准的7系列FPGA高性能I/O Bank进行连接 The I/Os in Xilinx® 7 series FPGAs are classified as either high range (HR) or high performance (HP) banks. HR I/O banks can be operated from 1.2V to 3.3V, whereas HP I/O banks are optimized for operation between 1.2V and 1.8V. In circumstances that require an HP 1.8V I/O bank to interface with 2.5V or 3.3V logic, a range of options can be deployed. This application note describes methodologies for interfacing 7 series HP I/O banks with 2.5V and 3.3V systems
上传时间： 2013-11-18
上传用户：yyyyyyyyyy
