===================================== GoAhead WebServer 2.1.8 Release Notes ===================================== .. NOTES: .. This document is maintained using the reStructuredText markup system. .. You may download this from <http://docutils.sf.net>. Also note that running .. the docutils code requires that a version of Python version 2.1 or later .. be installed on the machine. Since the GoAhead release procedure itself .. runs in Python, this should not be a problem. .. .. To add new entries to the release notes, follow the markup shown below .. (releases should be underlined with a row of '=' characters, each item .. noted within a release should be underlined with '-' characters.
上传时间： 2016-01-30
上传用户：zrxkn
===================================== GoAhead WebServer 2.1.8 Release Notes ===================================== .. NOTES: .. This document is maintained using the reStructuredText markup system. .. You may download this from <http://docutils.sf.net>. Also note that running .. the docutils code requires that a version of Python version 2.1 or later .. be installed on the machine. Since the GoAhead release procedure itself .. runs in Python, this should not be a problem. .. .. To add new entries to the release notes, follow the markup shown below .. (releases should be underlined with a row of '=' characters, each item .. noted within a release should be underlined with '-' characters.
标签： web html embed server arm small http
上传时间： 2016-01-30
上传用户：zrxkn
FPGA读写SD卡读取BMP图片通过LCD显示例程实验 Verilog逻辑源码Quartus工程文件+文档说明,FPGA型号Cyclone4E系列中的EP4CE6F17C8，Quartus版本17.1。1 实验简介在前面的实验中我们练习了 SD 卡读写，VGA 视频显示等例程，本实验将 SD 卡里的 BMP 图片读出，写入到外部存储器，再通过 VGA、LCD 等显示。本实验如果通过液晶屏显示，需要有液晶屏模块。2 实验原理在前面的实验中我们在 VGA、LCD 上显示的是彩条，是 FPGA 内部产生的数据，本实验将彩条替换为 SD 内的 BMP 图片数据，但是 SD 卡读取速度远远不能满足显示速度的要求，只能先写入外部高速 RAM，再读出后给视频时序模块显示module top( input clk, input rst_n, input key1, output [5:0] seg_sel, output [7:0] seg_data, output vga_out_hs, //vga horizontal synchronization output vga_out_vs, //vga vertical synchronization output[4:0] vga_out_r, //vga red output[5:0] vga_out_g, //vga green output[4:0] vga_out_b, //vga blue output sd_ncs, //SD card chip select (SPI mode) output sd_dclk, //SD card clock output sd_mosi, //SD card controller data output input sd_miso, //SD card controller data input output sdram_clk, //sdram clock output sdram_cke, //sdram clock enable output sdram_cs_n, //sdram chip select output sdram_we_n, //sdram write enable output sdram_cas_n, //sdram column address strobe output sdram_ras_n, //sdram row address strobe output[1:0] sdram_dqm, //sdram data enable output[1:0] sdram_ba, //sdram bank address output[12:0] sdram_addr, //sdram address inout[15:0] sdram_dq //sdram data);parameter MEM_DATA_BITS = 16 ; //external memory user interface data widthparameter ADDR_BITS = 24
标签： fpga
上传时间： 2021-10-27
上传用户：
AT89S52-24单片机最小系统开发板ALTIUM设计硬件原理图+PCB文件,2层板设计，大小为121x149mm，Altium Designer 设计的工程文件，包括完整的原理图及PCB文件，可以用Altium(AD)软件打开或修改，可作为你的产品设计的参考。主要器件型号列表如下：Library Component Count : 14Name Description----------------------------------------------------------------------------------------------------AT89S52-P 8 位微处理器/40引脚CAP CapacitorCAPACITOR POL CapacitorCRYSTAL CrystalD Connector 9 Receptacle Assembly, 9 Position, Right AngleHeader 2 Header, 2-PinHeader 4 Header, 4-PinHeader 5X2 Header, 5-Pin, Dual rowLED MAX232PZ_9 排针——9RES2SW-DPST Double-Pole, Single-Throw SwitchSW-PB Switch
上传时间： 2021-11-17
上传用户：
AT89S52单片机主8入8出继电器工控主板ALTIUM设计硬件原理图+PCB文件,2层板设计，大小为121x149mm，Altium Designer 设计的工程文件，包括完整的原理图及PCB文件，可以用Altium(AD)软件打开或修改，可作为你的产品设计的参考。主要器件型号列表如下：Library Component Count : 25Name Description----------------------------------------------------------------------------------------------------24LC02AJKG 按键开关AT89S52-P 8 位微处理器/40引脚CAP CapacitorCAPACITOR POL CapacitorCPDR 瓷片电容CRYSTAL CrystalD Connector 9 Receptacle Assembly, 9 Position, Right AngleDG 电感DJDR 电解电容GO 光耦Header 5X2 Header, 5-Pin, Dual rowJDQYCK 继电器——1常开1常闭LED 发光二极管LM2576HVT-3.3 Simple Switcher 3A Step Down Voltage RegulatorMAX232 NPN NPN Bipolar TransistorPZ_2 排针——2PZ_3 排针——3RES2Res 电阻Res PZ_8 8位排阻SW-DPST Double-Pole, Single-Throw SwitchWY2JG 稳压二级管ZL2JG 整流二极管
上传时间： 2021-11-17
上传用户：kingwide
STM32F407单片机开发板PDF原理图+AD集成封装库+主要器件技术手册资料:AD集成封装库列表：Library Component Count : 54Name Description----------------------------------------------------------------------------------------------------24C256 AMS1117ATK-HC05 ATK-HC05BAT BEEP BUTTONC CAPCH340G USB2UARTDDB9 DHT11 数字温湿度传感器HEAD2HEAD2*22 HR911105 HS0038Header 16 Header, 16-PinHeader 2 Header, 2-PinHeader 2X2 Header, 2-Pin, Dual rowHeader 3X2 Header, 3-Pin, Dual rowHeader 4 Header, 4-PinHeader 9X2 Header, 9-Pin, Dual rowIS62WV51216 JTAG KEY_M L LAN8720 ETH PHYLED2 Typical RED, GREEN, YELLOW, AMBER GaAs LEDLSENS LIGHT SENSL_SOP MAX3232 MAX3485 MIC MOS-P IRLML6401/SI2301MP2359 DC DC Step Down ICMPU6050 9轴运动处理传感器NPN 8050/BCW846/BCW847NRF24L01 PHONE_M PNP 8550/BCW68POW R SMBJ TVSSN65HVD230D STM32F407ZET6 STM32F407ZET6TEST-POINT 测试点TFT_LCD TPAD ALIENTEK TPADUSB5USB_A_90 USB-A-90W25X16
上传时间： 2021-12-15
上传用户：ttalli
FPGA读取OV5640摄像头数据并通过VGA或LCD屏显示输出的Verilog逻辑源码Quartus工程文件+文档说明，FPGA型号Cyclone4E系列中的EP4CE6F17C8，Quartus版本17.1。module top( input clk, input rst_n, output cmos_scl, //cmos i2c clock inout cmos_sda, //cmos i2c data input cmos_vsync, //cmos vsync input cmos_href, //cmos hsync refrence,data valid input cmos_pclk, //cmos pxiel clock output cmos_xclk, //cmos externl clock input [7:0] cmos_db, //cmos data output cmos_rst_n, //cmos reset output cmos_pwdn, //cmos power down output vga_out_hs, //vga horizontal synchronization output vga_out_vs, //vga vertical synchronization output[4:0] vga_out_r, //vga red output[5:0] vga_out_g, //vga green output[4:0] vga_out_b, //vga blue output sdram_clk, //sdram clock output sdram_cke, //sdram clock enable output sdram_cs_n, //sdram chip select output sdram_we_n, //sdram write enable output sdram_cas_n, //sdram column address strobe output sdram_ras_n, //sdram row address strobe output[1:0] sdram_dqm, //sdram data enable output[1:0] sdram_ba, //sdram bank address output[12:0] sdram_addr, //sdram address inout[15:0] sdram_dq //sdram data);
上传时间： 2021-12-18
上传用户：
基于FPGA设计的sdram读写测试实验Verilog逻辑源码Quartus工程文件+文档说明，DRAM选用海力士公司的 HY57V2562 型号,容量为的 256Mbit,采用了 54 引脚的TSOP 封装, 数据宽度都为 16 位, 工作电压为 3.3V,并丏采用同步接口方式所有的信号都是时钟信号。FPGA型号Cyclone4E系列中的EP4CE6F17C8，Quartus版本17.1。timescale 1ps/1psmodule top(input clk,input rst_n,output[1:0] led,output sdram_clk, //sdram clockoutput sdram_cke, //sdram clock enableoutput sdram_cs_n, //sdram chip selectoutput sdram_we_n, //sdram write enableoutput sdram_cas_n, //sdram column address strobeoutput sdram_ras_n, //sdram row address strobeoutput[1:0] sdram_dqm, //sdram data enable output[1:0] sdram_ba, //sdram bank addressoutput[12:0] sdram_addr, //sdram addressinout[15:0] sdram_dq //sdram data);parameter MEM_DATA_BITS = 16 ; //external memory user interface data widthparameter ADDR_BITS = 24 ; //external memory user interface address widthparameter BUSRT_BITS = 10 ; //external memory user interface burst widthparameter BURST_SIZE = 128 ; //burst sizewire wr_burst_data_req; // from external memory controller,write data request ,before data 1 clockwire wr_burst_finish; // from external memory controller,burst write finish
标签： fpga sdram verilog quartus
上传时间： 2021-12-18
上传用户：
黑金CYCLONE4 EP4CE6F17C8 FPGA开发板ALTIUM设计硬件工程（原理图+PCB+AD集成封装库）,Altium Designer 设计的工程文件，包括完整的原理图及PCB文件，可以用Altium(AD)软件打开或修改，可作为你产品设计的参考。集成封装器件型号列表：Library Component Count : 50Name Description----------------------------------------------------------------------------------------------------1117-3.3 24LC04B_0 4148 BAV99 CAP NP_Dup2CAP NP_Dup2_1 CAP NP_Dup2_2CP2102_0 C_Dup1 C_Dup1_1C_Dup2 C_Dup3 C_Dup4 C_Dup4_1 Circuit Breaker Circuit BreakerConnector 15 Receptacle Assembly, 15-Pin, Sim Line ConnectorDS1302_8SO EC EP4CE6F17C8 Cyclone IV Family FPGA, 2V Core, 179 I/O Pins, 2 PLLs, 256-Pin FBGA, Speed Grade 8, Commercial GradeEP4CE6F17C8_1 Cyclone IV Family FPGA, 2V Core, 179 I/O Pins, 2 PLLs, 256-Pin FBGA, Speed Grade 8, Commercial GradeFuse 2 FuseHEX6HY57651620/SO_0 Header 2 Header, 2-PinHeader 9X2 Header, 9-Pin, Dual rowINDUCTOR JTAG-10_Dup1 KEYB LED LED_Dup1 M25P16-VMN3PB 16 Mb (x1) Automotive Serial NOR Flash Memory, 75 MHz, 2.7 to 3.6 V, 8-pin SO8 Narrow (MN), TubeMHDR2X20 Header, 20-Pin, Dual rowMiniUSBB OSCPNP R RESISTOR RN RN_Dup1 R_Dup1 R_Dup2 R_Dup3 R_Dup5R_Dup6 SD SPEAKERSRV05-4SW KEY-DPDT ZTAbattery
标签： 黑金 cyclone4 ep4ce6f17c8 fpga
上传时间： 2021-12-22
上传用户：
TMS320F28035 DSP最小核心板开发板ALTIUM设计原理图，无PCB板图。原理图已在项目中使用，包括CAN通信电路和瓷隔离电路等，可以做为你的设计参考，所用器件型号如下：ADUM1201AT24CXXBAV99 R26010005CAP CapacitorHeader 4 Header, 4-PinHeader 4X2 Header, 4-Pin, Dual rowINDUCTORL2 LM317 R25040043NTC R27040030OPTOISORES R20190049RES1 SN65HVD230/SO8SW-SPST Single-Pole, Single-Throw SwitchTL431TMS320F28035-80XTAL Crystal Oscillator
标签： tms320f28035 dsp
上传时间： 2021-12-22
上传用户：trh505
