register mapping

This Telecommunication Standard [TS] describes the detailed mapping from input blocks of 160 speech

This Telecommunication Standard [TS] describes the detailed mapping from input blocks of 160 speech samples in 13-bit ...

JILRuntime A general purpose, register based virtual machine (VM) that supports object-oriented feat

JILRuntime A general purpose, register based virtual machine (VM) that supports object-oriented features, reference coun...

Flash中内置了一个状态寄存器（Status Register

Flash中内置了一个状态寄存器（Status Register，SR）来指示Flash的当前工作状态和各种操作是否成功。要读取SR的当前值需要向CUI发送读状态寄存器命令（Read Status Register），命令码为0x70，SR...

Mapper for QAM 2,4 and 6 bits, taking streams and mapping 2 symbols for Modulation

Mapper for QAM 2,4 and 6 bits, taking streams and mapping 2 symbols for Modulation...

atmel at91sam7s header file extented, some extra register definitions are set and extra functions ar

atmel at91sam7s header file extented, some extra register definitions are set and extra functions are dinifined...

Code for devellop for most DSP application. This code includes configurations for register into the

Code for devellop for most DSP application. This code includes configurations for register into the CPU easy to adapt....

Genesis Microchip Inc. LCD controller chip configuration and debugging tool this is a Register dat

Genesis Microchip Inc. LCD controller chip configuration and debugging tool this is a Register database for Genesis gm...

calculates Linear Feedback Shift Register(LFSR) mask and seed values for a specific phase shift.

calculates Linear Feedback Shift Register(LFSR) mask and seed values for a specific phase shift....

Face Transfer is a method for mapping videorecorded perfor-mances of one individual to facial animat

Face Transfer is a method for mapping videorecorded perfor-mances of one individual to facial animations of another. It ...

IEEE Std 1364.1-2002 IEEE Std. 1364.1 - 2002 IEEE Standard for Verilog Register Transfer Level Synth

IEEE Std 1364.1-2002 IEEE Std. 1364.1 - 2002 IEEE Standard for Verilog Register Transfer Level Synthesis.rar...