·详细说明:对彩色车牌图象的截取与识别 包括灰度化,均衡,除噪.截取等文件列表: 车牌识辨源程序 ..............\Debug ..............\ReadMe.txt ..............\Reconize.aps ..............\Reconize.clw .......
上传时间: 2013-04-24
上传用户:waitingfy
LPC178* 177*用户手册 LPC178x/7x 32-bit ARM Cortex-M3 microcontroller; up to 512 kB flash and 96 kB SRAM; USB Device/Host/OTG; Ethernet; LCD; EMC Rev. 3 — 27 December 2011 Objective data sheet
上传时间: 2013-04-24
上传用户:胡佳明胡佳明
olfile readme file. [1. 文件名解释] olfile: Offload File 这个工具原本是项目中为测试TOE引擎的效率而设计的, 可以作为socket编程的一个例子来学习。 [2. 文件介绍] 程序中使用socket实现了文件的传输。
上传时间: 2013-05-24
上传用户:ryb
MSP430FR57xx Family User's Guide (Rev. A)
上传时间: 2013-11-15
上传用户:ainimao
msp430单片机
标签: Erratasheet 14x x14 Device
上传时间: 2013-10-19
上传用户:dick_sh
TI公司低功耗单片机MSP430系列。
标签: MSP 430 Microcontroller Signal
上传时间: 2013-11-23
上传用户:非衣2016
24cxx读写程序软件-中文版 版本:V1.1.0.20916增加功能:用户可以设置并口地址 可以编辑Client区内容 修改了Client区界面 简体中文,英文双语界面 详见安装好后的Readme.pdf-----------------------------------说明:W24CXX.EXE为Windwos下使用计算机并口读写24系列I2C EEPROM的小软件开发工具:Borland C++ Builder 6.0 WinDriver 5.05b开发环境:Windows 2K Profressional SP3运行环境:Windows98/NT/2K/XP-----------------------------------程序开发:林晓斌(SONICSS)EMAIL: SONICSS@CNUNINET.COM注:若您使用Win98系统,必须重新启动计算机
上传时间: 2013-11-10
上传用户:wxnumen
This application note covers the design considerations of a system using the performance features of the LogiCORE™ IP Advanced eXtensible Interface (AXI) Interconnect core. The design focuses on high system throughput through the AXI Interconnect core with F MAX and area optimizations in certain portions of the design. The design uses five AXI video direct memory access (VDMA) engines to simultaneously move 10 streams (five transmit video streams and five receive video streams), each in 1920 x 1080p format, 60 Hz refresh rate, and up to 32 data bits per pixel. Each VDMA is driven from a video test pattern generator (TPG) with a video timing controller (VTC) block to set up the necessary video timing signals. Data read by each AXI VDMA is sent to a common on-screen display (OSD) core capable of multiplexing or overlaying multiple video streams to a single output video stream. The output of the OSD core drives the DVI video display interface on the board. Performance monitor blocks are added to capture performance data. All 10 video streams moved by the AXI VDMA blocks are buffered through a shared DDR3 SDRAM memory and are controlled by a MicroBlaze™ processor. The reference system is targeted for the Virtex-6 XC6VLX240TFF1156-1 FPGA on the Xilinx® ML605 Rev D evaluation board
上传时间: 2013-11-14
上传用户:fdmpy
ZBT SRAM控制器参考设计,xilinx提供VHDL代码 Description: Contains the following files readme.txt appnote_zbtp.vhd appnote_zbtf.vhd appnote_zbt.ucf Platform: All Installation/Use: Use 'unzip' on the .zip file and 'gunzip' followed by 'tar -xvf' on the .tar.gz file.
上传时间: 2013-11-24
上传用户:31633073
ref-sdr-sdram-vhdl代码 SDR SDRAM Controller v1.1 readme.txt This readme file for the SDR SDRAM Controller includes information that was not incorporated into the SDR SDRAM Controller White Paper v1.1. The PLL is targeted at APEX(TM) devices. Please regenerate for your chosen architecture. Last updated September, 2002 Copyright ?2002 Altera Corporation. All rights reserved.
上传时间: 2013-11-13
上传用户:takako_yang