vhdl work "Plus60.vhf" vhdl work "Hour.vhf" vhdl work "alarm.vhf" vhdl work "CLOCK.vhf"
primer+plus 源代码
汇集 primer+plus 相关的电路原理图、PCB工程文件、单片机/FPGA源代码、数据手册与应用设计方案。
set allSynthModules {Plus60.MOD Hour.MOD alarm.MOD CLOCK.MOD}
/usr/lib/gcc-lib/i486-linux/2.7.2.3/cc1plus
/usr/lib/gcc-lib/i486-linux/2.7.2.3/cc1plus
/usr/lib/gcc-lib/i486-linux/2.7.2.3/cc1plus
c:\ORAWIN95\BIN\plus33 system/manager @c:\srvinst\install
//! //!----------------------------------------------------------------------------- //! Name IEUDef.PAS //! …
[General Information] 书名=CPLD数字电路设计——使用MAX+plusⅡ入门篇 作者= 页数=551 SS号=0 下载位置=http://192.168.36.205/01/disknjs/njs164/03/!00001.p…
Synthesizing work.counter2plus.behavioral Post processing for work.counter2plus.behavioral
/usr/lib/gcc-lib/i486-linux/2.7.2.3/cc1plus