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单片机开发 These routines transmit and receive serial data using two general * I/O pins, in 8 bit, No parity,
These routines transmit and receive serial data using two general
* I/O pins, in 8 bit, No parity, 1 stop bit format. They are useful
* for performing serial I/O on 8051 derivatives not having an
* internal UART, or for implementing a second serial channel.
软件设计/软件工程 When the P89LPC90x is in programming mode all pins that are not used for programming are tri-stated.
When the P89LPC90x is in programming mode all pins that are not used for programming are tri-stated. During
programming mode the reset pin has a weak pull-up resistor.
行业发展研究 SCART接口的定义和功能介绍。Special pins on EURO_SCART
SCART接口的定义和功能介绍。Special pins on EURO_SCART
单片机开发 富士通单片机MB902420系列 extINT Project: All external Interrupt-Pins INT0 .. INT7 will be enabled. A fall
富士通单片机MB902420系列
extINT Project:
All external Interrupt-Pins INT0 .. INT7 will be enabled.
A falling edge on INTx will toggle PDR4_P4x
in order to toggle the LEDx of the Flash-CAN-100P Board
e.g. falling edge on INT3 will result in LED D3 will toggleP47..P40 (UserLEDs of FlashCan100P)
and ...
单片机开发 wsd:enc28j60 28 pins for ethernet design,10Mbps,enc28j60+avr chip m16 webserver source.
wsd:enc28j60 28 pins for ethernet design,10Mbps,enc28j60+avr chip m16 webserver source.
Java书籍 This software transmits data (using TCP/IP) from I/O pins (of the Tini Board - from Dallas Semicondu
This software transmits data (using TCP/IP) from I/O pins (of the Tini Board - from Dallas Semiconductors) to a specific IP address.
单片机开发 Device pins that are not connected to a specific peripheral function are controlled by the GPIO reg
Device pins that are not connected to a specific peripheral function are controlled by the
GPIO registers. Pins may be dynamically configured as inputs or outputs. Separate
registers allow setting or clearing any number of outputs simu
中文
VHDL/FPGA/Verilog Top module name : SHIFTER (File name : SHIFTER.v) 2. Input pins: SHIFT [3:0], IN [15:0], SIGN, RIGH
Top module name : SHIFTER (File name : SHIFTER.v)
2. Input pins: SHIFT [3:0], IN [15:0], SIGN, RIGHT.
3. Output pins: OUT [15:0].
4. Input signals generated from test pattern are latched in one cycle and are
synchronized at clock rising edge.
5. The SHIFT signal describes the shift number. The shift ...
VHDL/FPGA/Verilog Top module name : SHIFTER (File name : SHIFTER.v) 2. Input pins: SHIFT [3:0], IN [15:0], SIGN, RIGH
Top module name : SHIFTER (File name : SHIFTER.v)
2. Input pins: SHIFT [3:0], IN [15:0], SIGN, RIGHT.
3. Output pins: OUT [15:0].
4. Input signals generated from test pattern are latched in one cycle and are
synchronized at clock rising edge.
5. The SHIFT signal describes the shift number. The shift ...
编译器/解释器 this is a stepper motor controller with specifications pins: for RS-232 interfacing stepper motor:
this is a stepper motor controller with specifications pins: for RS-232 interfacing
stepper motor: 47-50 bus
PUSH button: 9-15
POTEN:9-15