The Motorola MPC106 PCI bridge/memory controller provides a PowerPCªmicroprocessor common hardware reference platform (CHRPª) compliant bridgebetween the PowerPC microprocessor family and the Peripheral Component Interconnect(PCI) bus. In this document, the term Ô106Õ is used as an abbreviation for the phraseÔMPC106 PCI bridge/memory controllerÕ. This document contains pertinent physicalcharacteristics of the 106. For functional characteristics refer to theMPC106 PCI Bridge/Memory Controller UserÕs Manual.This document contains the following topics:Topic PageSection 1.1, ÒOverviewÓ 2Section 1.2, ÒFeaturesÓ 3Section 1.3, ÒGeneral ParametersÓ 5Section 1.4, ÒElectrical and Thermal CharacteristicsÓ 5Section 1.5, ÒPin AssignmentsÓ 17Section 1.6, ÒPinout Listings 18Section 1.7, ÒPackage DescriptionÓ 22Section 1.8, ÒSystem Design InformationÓ 24Section 1.9, ÒDocument Revision HistoryÓ 29Section 1.10, ÒOrdering InformationÓ 29
上传时间： 2013-11-04
上传用户：as275944189
基于P87 C591的CAN总线系统智能节点设计Design of CAN System Intelligent Node Based on P87C591 给出了基于带CAN控制器的单片8位微控制器P87C591的智能节点的硬件电路及软件结构，详细介绍了设计中的难点及实现过程中应注意的问题。关键词:CAN总线;智能节点 Abstract:A h ardc ircuita nds oftw arec onfigurationo fth ei ntelligentnode based on a microcontroller with CAN controller P87C591 arepresented.E speciallyt hec ruxi nd esigninga ndt hep roblemst hatshould be paid attention in realizing are discussed in details.Keyw ords:C AN;in telligentn ode CA N 总线 是德国Bosch从20世纪80年代初为解决现代汽车中众多的控制与测试仪器之间的数据交换而开发的一种串行数据通信协议，它是一种多主总线，通信介质可以是双绞线、同轴电缆或光导纤维。由于CAN总线具有较强的纠错能力，支持差分收发，因而适合高噪声环境。并具有较远的传输距离，适用于许多领域的分布式测控系统。目前已在工业自动化、建筑物环境控制、医疗设备等许多领域得到广泛的应用。CAN已成为国际标准化组织IS011898标准。
上传时间： 2013-10-30
上传用户：xymbian
提出了一个由AT89C52单片机控制步进电机的实例。可以通过键盘输入相关数据, 并根据需要, 实时对步进电机工作方式进行设置, 具有实时性和交互性的特点。该系统可应用于步进电机控制的大多数场合。实践表明, 系统性能优于传统的步进电机控制器。关键词: 单片机; 步进电动机; 直流固态继电器; 实时控制Con trol System of Stepp ingMotor Ba sed on AT89C52 ChipM icrocomputerMENGWu2sheng, L ILiang (College of Automatization, Northwestern Polytechnical Unversity, Xipan 710072, China)ABSTRACT: A stepp ing motor control system based on AT89C52 chip microcomputer was described.The data can be inputwith keyboard, and stepp ingmotorwas controlled by these data. According to the demand, users can set the workingmodel of stepp ingmotor in real2time. This system can be widely used in stepp ing motor controlling. The p ractice showed that the performance of this system outdid the tradi tional stepp ing motor controller.KEY WORDS: Chip microcomputer; Stepp ingmotor; DCSSR; Real2time control
标签： Control System ingMot Stepp
上传时间： 2013-11-19
上传用户：leesuper
一种基于ST62单片机的称重显示控制器A Weighing Display Controller Based on ST62 Single Chip Computer祛 FA(上海时博飞奥控制系统有限公司，上海201100)摘要在介绍了基于ST62单片机的基础上，详细描述了称重显控制器的硬件设计和软件设计思路。该控制器结构简单、操作方便、抗扰能力强等优点;具有较好的推广应用价值。关键词称重显示控制仪ST62单片机硬件设计软件设计Abstract Ont heb asiso fin torductiono fST 62s inglec hipc omputer,th ed esignc oncrptof h ardwarea nds oftwarefo rw eighingd isplayc ontorleris d escrbed.The controler features simple structure, ease operation, powerful capability of anti-interference, etc.，it is wealth to be promoted into practicalapplicationsKeywords We妙吨display0 引言ST62s inglec hip Hardwared esign Softwaer design备 份 振 荡器，振荡器保护电路，上电复位及低压检测复称 重 显 示控制器是一种具有数字显示、开关量输出、定值控制和通信功能的以微机为操作核心的称重控制装置。它是电子衡器的重要基础部件，直接影响电子衡器及电子称重系统的功能和性能。与合适的传感器及承重传力复位系统组合可组成配料秤、料斗秤、定值秤、平台秤、汽车秤等，广泛应用于电力、化工、建筑、冶金、交通运输、食品、军工等部门，是进行自动称重配料控制和生产过程自动化必不可少的重要检测、控制装置。随着 称 重 计量自动化水平的提高，对称重显示控制器的要求也越来越高。为实现低漂移、高稳定，本控制器采用低漂移、高增益放大器AD620和高分辨率的A/D转换器CS5550。为提高稳定性和可靠性，采用集成度高的、抗干扰能力强的ST62单片机。
上传时间： 2013-10-29
上传用户：钓鳌牧马
This application note shows how to achieve low-cost, efficient serial configuration for Spartan FPGA designs. The approachrecommended here takes advantage of unused resources in a design, thereby reducing the cost, part count, memory size,and board space associated with the serial configuration circuitry. As a result, neither processor nor PROM needs to be fullydedicated to performing Spartan configuration.In particular, information is provided on how the idle processing time of an on-board controller can be used to loadconfiguration data from an off-board source. As a result, it is possible to upgrade a Spartan design in the field by sending thebitstream over a network.
上传时间： 2014-08-16
上传用户：adada
This application note describes how to build a system that can be used for determining theoptimal phase shift for a Double Data Rate (DDR) memory feedback clock. In this system, theDDR memory is controlled by a controller that attaches to either the OPB or PLB and is used inan embedded microprocessor application. This reference system also uses a DCM that isconfigured so that the phase of its output clock can be changed while the system is running anda GPIO core that controls that phase shift. The GPIO output is controlled by a softwareapplication that can be run on a PowerPC® 405 or Microblaze™ microprocessor.
上传时间： 2013-10-15
上传用户：euroford
The PLB BRAM Interface Controller is a module thatattaches to the PLB (Processor Local Bus).
上传时间： 2013-10-27
上传用户：zoudejile
This application note covers the design considerations of a system using the performance features of the LogiCORE™ IP Advanced eXtensible Interface (AXI) Interconnect core. The design focuses on high system throughput through the AXI Interconnect core with F MAX and area optimizations in certain portions of the design. The design uses five AXI video direct memory access (VDMA) engines to simultaneously move 10 streams (five transmit video streams and five receive video streams), each in 1920 x 1080p format, 60 Hz refresh rate, and up to 32 data bits per pixel. Each VDMA is driven from a video test pattern generator (TPG) with a video timing controller (VTC) block to set up the necessary video timing signals. Data read by each AXI VDMA is sent to a common on-screen display (OSD) core capable of multiplexing or overlaying multiple video streams to a single output video stream. The output of the OSD core drives the DVI video display interface on the board. Performance monitor blocks are added to capture performance data. All 10 video streams moved by the AXI VDMA blocks are buffered through a shared DDR3 SDRAM memory and are controlled by a MicroBlaze™ processor. The reference system is targeted for the Virtex-6 XC6VLX240TFF1156-1 FPGA on the Xilinx® ML605 Rev D evaluation board
上传时间： 2013-11-14
上传用户：fdmpy
ref-sdr-sdram-vhdl代码 SDR SDRAM Controller v1.1 readme.txt This readme file for the SDR SDRAM Controller includes information that was not incorporated into the SDR SDRAM Controller White Paper v1.1. The PLL is targeted at APEX(TM) devices. Please regenerate for your chosen architecture. Last updated September, 2002 Copyright ?2002 Altera Corporation. All rights reserved.
上传时间： 2013-11-13
上传用户：takako_yang
a8259 可编程中断控制 altera提供 The a8259 is designed to simplify the implementation of the interrupt interface in 8088 and 8086 based microcomputer systems. The device is known as a programmable interrupt controller. The a8259 receives and prioritizes up to 8 interrupts, and in the cascade mode, this can be expanded up to 64 interrupts. An asynchronous reset and a clock input have been added to improve operation and reliability.
上传时间： 2014-11-29
上传用户：zhyiroy
