Finite state machines are widely used in digital circuit designs. Generally, when designing a state machine using an HDL, the synthesis tools will optimize away all states that cannot be reached and generate a highly optimized circuit. Sometimes, however, the optimization is not acceptable. For example, if the circuit powers up in an invalid state, or the circuit is in an extreme working environment and a glitch sends it into an undesired state, the circuit may never get back to its normal operating condition.
标签： Creating Machines Mentor State
上传时间： 2013-10-08
上传用户：wangzhen1990
DC-link Automotive: MKP1849 (Customized)电动汽车电驱直流母线电容（顾客订制品）MKP1849系列.MKP1849-可集成母线排，大大降低了寄生电感，提高了系统稳定性。
上传时间： 2013-10-13
上传用户：nanfeicui
J-Link V8个人使用经验写成的用户手册
上传时间： 2013-10-07
上传用户：hulee
教你如何制作一个J-Link V8仿真器！ 已经成功！
上传时间： 2013-10-15
上传用户：truth12
介绍一种人机交互系统的可靠性设计方案。该系统基于Memory-link通信协议，采用了目前流行的基于ARM7架构的S3C44BOX作为主控芯片，通过RS-422实现人机交互通信。结合抗干扰的硬件设计和稳定有效运行的软件设计方案，实现了在强干扰下稳定可靠的通信。实验结果表明，本系统抗干扰能力强、运行稳定可靠，在自主开发控制系统的人机交互通信部分具有一定的参考价值。
标签： Memory-link 协议 人机交互系统 可靠性设计
上传时间： 2013-11-21
上传用户：cknck
J-LINK仿真器详细教程 flash下载操作等
上传时间： 2013-11-14
上传用户：JamesB
本文主要介绍MDK4.10下，连接ST-Link II的设置方法，给出了所有所需的配置文件。
上传时间： 2013-11-22
上传用户：kang1923
本文论述了状态机的verilog编码风格,以及不同编码风格的优缺点，Steve Golson's 1994 paper, "State Machine Design Techniques for Verilog and VHDL" [1], is agreat paper on state machine design using Verilog, VHDL and Synopsys tools. Steve's paper alsooffers in-depth background concerning the origin of specific state machine types.This paper, "State Machine Coding Styles for Synthesis," details additional insights into statemachine design including coding style approaches and a few additional tricks.
标签： Synthesis Machine Coding Styles
上传时间： 2013-10-12
上传用户：sardinescn
One of the strengths of Synplify is the Finite State Machine compiler. This is a powerfulfeature that not only has the ability to automatically detect state machines in the sourcecode, and implement them with either sequential, gray, or one-hot encoding. But alsoperform a reachability analysis to determine all the states that could possibly bereached, and optimize away all states and transition logic that can not be reached.Thus, producing a highly optimal final implementation of the state machine.
标签： Synplicity Machine Verilog Design
上传时间： 2013-10-20
上传用户：苍山观海
Finite state machines are widely used in digital circuit designs. Generally, when designing a state machine using an HDL, the synthesis tools will optimize away all states that cannot be reached and generate a highly optimized circuit. Sometimes, however, the optimization is not acceptable. For example, if the circuit powers up in an invalid state, or the circuit is in an extreme working environment and a glitch sends it into an undesired state, the circuit may never get back to its normal operating condition.
标签： Creating Machines Mentor State
上传时间： 2013-11-02
上传用户：xauthu
