The μPSD32xx family, from ST, consists of Flash programmable system devices with a 8032 MicrocontrollerCore. Of these, the μPSD3234A and μPSD3254A are notable for having a complete implementationof the USB hardware directly on the chip, complying with the Universal Serial Bus Specification, Revision1.1.This application note describes a demonstration program that has been written for the DK3200 hardwaredemonstration kit (incorporating a μPSD3234A device). It gives the user an idea of how simple it is to workwith the device, using the HID class as a ready-made device driver for the USB connection.IN-APPLICATION-PROGRAMMING (IAP) AND IN-SYSTEM-PROGRAMMING (ISP)Since the μPSD contains two independent Flash memory arrays, the Micro Controller Unit (MCU) can executecode from one memory while erasing and programming the other. Product firmware updates in thefield can be reliably performed over any communication channel (such as CAN, Ethernet, UART, J1850)using this unique architecture. For In-Application-Programming (IAP), all code is updated through theMCU. The main advantage for the user is that the firmware can be updated remotely. The target applicationruns and takes care on its own program code and data memory.IAP is not the only method to program the firmware in μPSD devices. They can also be programmed usingIn-System-Programming (ISP). A IEEE1149.1-compliant JTAG interface is included on the μPSD. Withthis, the entire device can be rapidly programmed while soldered to the circuit board (Main Flash memory,Secondary Boot Flash memory, the PLD, and all configuration areas). This requires no MCU participation.The MCU is completely bypassed. So, the μPSD can be programmed or reprogrammed any time, anywhere, even when completely uncommitted.Both methods take place with the device in its normal hardware environment, soldered to a printed circuitboard. The IAP method cannot be used without previous use of ISP, because IAP utilizes a small amountof resident code to receive the service commands, and to perform the desired operations.
标签： Demonstration 3200 USB for
上传时间： 2014-02-27
上传用户：zhangzhenyu
All inputs of the C16x family have Schmitt-Trigger input characteristics. These Schmitt-Triggers are intended to always provide proper internal low and high levels, even if anundefined voltage level (between TTL-VIL and TTL-VIH) is externally applied to the pin.The hysteresis of these inputs, however, is very small, and can not be properly used in anapplication to suppress signal noise, and to shape slow rising/falling input transitions.Thus, it must be taken care that rising/falling input signals pass the undefined area of theTTL-specification between VIL and VIH with a sufficient rise/fall time, as generally usualand specified for TTL components (e.g. 74LS series: gates 1V/us, clock inputs 20V/us).The effect of the implemented Schmitt-Trigger is that even if the input signal remains inthe undefined area, well defined low/high levels are generated internally. Note that allinput signals are evaluated at specific sample points (depending on the input and theperipheral function connected to it), at that signal transitions are detected if twoconsecutive samples show different levels. Thus, only the current level of an input signalat these sample points is relevant, that means, the necessary rise/fall times of the inputsignal is only dependant on the sample rate, that is the distance in time between twoconsecutive evaluation time points. If an input signal, for instance, is sampled throughsoftware every 10us, it is irrelevant, which input level would be seen between thesamples. Thus, it would be allowable for the signal to take 10us to pass through theundefined area. Due to the sample rate of 10us, it is assured that only one sample canoccur while the signal is within the undefined area, and no incorrect transition will bedetected. For inputs which are connected to a peripheral function, e.g. capture inputs, thesample rate is determined by the clock cycle of the peripheral unit. In the case of theCAPCOM unit this means a sample rate of 400ns @ 20MHz CPU clock. This requiresinput signals to pass through the undefined area within these 400ns in order to avoidmultiple capture events.For input signals, which do not provide the required rise/fall times, external circuitry mustbe used to shape the signal transitions.In the attached diagram, the effect of the sample rate is shown. The numbers 1 to 5 in thediagram represent possible sample points. Waveform a) shows the result if the inputsignal transition time through the undefined TTL-level area is less than the time distancebetween the sample points (sampling at 1, 2, 3, and 4). Waveform b) can be the result ifthe sampling is performed more than once within the undefined area (sampling at 1, 2, 5,3, and 4).Sample points:1. Evaluation of the signal clearly results in a low level2. Either a low or a high level can be sampled here. If low is sampled, no transition willbe detected. If the sample results in a high level, a transition is detected, and anappropriate action (e.g. capture) might take place.3. Evaluation here clearly results in a high level. If the previous sample 2) had alreadydetected a high, there is no change. If the previous sample 2) showed a low, atransition from low to high is detected now.
上传时间： 2013-10-23
上传用户：copu
All inputs of the C16x family have Schmitt-Trigger input characteristics. These Schmitt-Triggers are intended to always provide proper internal low and high levels, even if anundefined voltage level (between TTL-VIL and TTL-VIH) is externally applied to the pin.The hysteresis of these inputs, however, is very small, and can not be properly used in anapplication to suppress signal noise, and to shape slow rising/falling input transitions.Thus, it must be taken care that rising/falling input signals pass the undefined area of theTTL-specification between VIL and VIH with a sufficient rise/fall time, as generally usualand specified for TTL components (e.g. 74LS series: gates 1V/us, clock inputs 20V/us).The effect of the implemented Schmitt-Trigger is that even if the input signal remains inthe undefined area, well defined low/high levels are generated internally. Note that allinput signals are evaluated at specific sample points (depending on the input and theperipheral function connected to it), at that signal transitions are detected if twoconsecutive samples show different levels. Thus, only the current level of an input signalat these sample points is relevant, that means, the necessary rise/fall times of the inputsignal is only dependant on the sample rate, that is the distance in time between twoconsecutive evaluation time points. If an input signal, for instance, is sampled throughsoftware every 10us, it is irrelevant, which input level would be seen between thesamples. Thus, it would be allowable for the signal to take 10us to pass through theundefined area. Due to the sample rate of 10us, it is assured that only one sample canoccur while the signal is within the undefined area, and no incorrect transition will bedetected. For inputs which are connected to a peripheral function, e.g. capture inputs, thesample rate is determined by the clock cycle of the peripheral unit. In the case of theCAPCOM unit this means a sample rate of 400ns @ 20MHz CPU clock. This requiresinput signals to pass through the undefined area within these 400ns in order to avoidmultiple capture events.
上传时间： 2014-04-02
上传用户：han_zh
The MC68HC05K0 is a low cost, low pin countsingle chip microcomputer with 504 bytes of userROM and 32 bytes of RAM. The MC68HC05K0 isa member of the 68HC05K series of devices whichare available in 16-pin DIL or SOIC packages.It uses the same CPU as the other devices in the68HC05 family and has the same instructions andregisters. Additionally, the device has a 15-stagemulti-function timer and 10 general purposebi-directional I/0 lines. A mask option is availablefor software programmable pull-downs on all ofthe I/O pins and four of the pins are capable ofgenerating interrupts.The device is ideally suited for remote-controlkeyboard applications because the pull-downs andthe interrupt drivers on the port pins allowkeyboards to be built without any externalcomponents except the keys themselves. There isno need for external pull-up or pull-down resistors,or diodes for wired-OR interrupts, as these featuresare already designed into the device.
上传时间： 2014-01-24
上传用户：zl5712176
有两种方式可以让设备和应用程序之间联系：1. 通过为设备创建的一个符号链；2. 通过输出到一个接口WDM驱动程序建议使用输出到一个接口而不推荐使用创建符号链的方法。这个接口保证PDO的安全，也保证安全地创建一个惟一的、独立于语言的访问设备的方法。一个应用程序使用Win32APIs来调用设备。在某个Win32 APIs和设备对象的分发函数之间存在一个映射关系。获得对设备对象访问的第一步就是打开一个设备对象的句柄。 用符号链打开一个设备的句柄为了打开一个设备，应用程序需要使用CreateFile。如果该设备有一个符号链出口，应用程序可以用下面这个例子的形式打开句柄：hDevice = CreateFile("\\\\.\\OMNIPORT3", GENERIC_READ | GENERIC_WRITE,FILE_SHARE_READ, NULL, OPEN_EXISTING, FILE_ATTRIBUTE_NORMAL ,NULL);文件路径名的前缀“\\.\”告诉系统本调用希望打开一个设备。这个设备必须有一个符号链，以便应用程序能够打开它。有关细节查看有关Kdevice和CreateLink的内容。在上述调用中第一个参数中前缀后的部分就是这个符号链的名字。注意：CreatFile中的第一个参数不是Windows 98/2000中驱动程序(.sys文件)的路径。是到设备对象的符号链。如果使用DriverWizard产生驱动程序，它通常使用类KunitizedName来构成设备的符号链。这意味着符号链名有一个附加的数字，通常是0。例如：如果链接名称的主干是L“TestDevice”那么在CreateFile中的串就该是“\\\\.\\TestDevice0”。如果应用程序需要被覆盖的I/O，第六个参数(Flags)必须或上FILE_FLAG_OVERLAPPED。 使用一个输出接口打开句柄用这种方式打开一个句柄会稍微麻烦一些。DriverWorks库提供两个助手类来使获得对该接口的访问容易一些，这两个类是CDeviceInterface, 和 CdeviceInterfaceClass。CdeviceInterfaceClass类封装了一个设备信息集，该信息集包含了特殊类中的所有设备接口信息。应用程序能有用CdeviceInterfaceClass类的一个实例来获得一个或更多的CdeviceInterface类的实例。CdeviceInterface类是一个单一设备接口的抽象。它的成员函数DevicePath()返回一个路径名的指针，该指针可以在CreateFile中使用来打开设备。下面用一个小例子来显示这些类最基本的使用方法：extern GUID TestGuid;HANDLE OpenByInterface( GUID* pClassGuid, DWORD instance, PDWORD pError){ CDeviceInterfaceClass DevClass(pClassGuid, pError); if (*pError != ERROR_SUCCESS) return INVALID_HANDLE_VALUE; CDeviceInterface DevInterface(&DevClass, instance, pError); if (*pError != ERROR_SUCCESS) return INVALID_HANDLE_VALUE; cout << "The device path is " << DevInterface.DevicePath() << endl; HANDLE hDev; hDev = CreateFile( DevInterface.DevicePath(), GENERIC_READ | GENERIC_WRITE, FILE_SHARE_READ | FILE_SHARE_WRITE, NULL, OPEN_EXISTING, FILE_ATTRIBUTE_NORMAL, NULL ); if (hDev == INVALID_HANDLE_VALUE) *pError = GetLastError(); return hDev;} 在设备中执行I/O操作一旦应用程序获得一个有效的设备句柄，它就能使用Win32 APIs来产生到设备对象的IRPs。下面的表显示了这种对应关系。Win32 API DRIVER_FUNCTION_xxxIRP_MJ_xxx KDevice subclass member function CreateFile CREATE Create ReadFile READ Read WriteFile WRITE Write DeviceIoControl DEVICE_CONTROL DeviceControl CloseHandle CLOSECLEANUP CloseCleanUp 需要解释一下设备类成员的Close和CleanUp：CreateFile使内核为设备创建一个新的文件对象。这使得多个句柄可以映射同一个文件对象。当这个文件对象的最后一个用户级句柄被撤销后，I/O管理器调用CleanUp。当没有任何用户级和核心级的对文件对象的访问的时候，I/O管理器调用Close。如果被打开的设备不支持指定的功能，则调用相应的Win32将引起错误（无效功能）。以前为Windows95编写的VxD的应用程序代码中可能会在打开设备的时候使用FILE_FLAG_DELETE_ON_CLOSE属性。在Windows NT/2000中，建议不要使用这个属性，因为它将导致没有特权的用户企图打开这个设备，这是不可能成功的。I/O管理器将ReadFile和WriteFile的buff参数转换成IRP域的方法依赖于设备对象的属性。当设备设置DO_DIRECT_IO标志，I/O管理器将buff锁住在存储器中，并且创建了一个存储在IRP中的MDL域。一个设备可以通过调用Kirp::Mdl来存取MDL。当设备设置DO_BUFFERED_IO标志，设备对象分别通过KIrp::BufferedReadDest或 KIrp::BufferedWriteSource为读或写操作获得buff地址。当设备不设置DO_BUFFERED_IO标志也不设置DO_DIRECT_IO，内核设置IRP 的UserBuffer域来对应ReadFile或WriteFile中的buff参数。然而，存储区并没有被锁住而且地址只对调用进程有效。驱动程序可以使用KIrp::UserBuffer来存取IRP域。对于DeviceIoControl调用，buffer参数的转换依赖于特殊的I/O控制代码，它不在设备对象的特性中。宏CTL_CODE（在winioctl.h中定义）用来构造控制代码。这个宏的其中一个参数指明缓冲方法是METHOD_BUFFERED, METHOD_IN_DIRECT, METHOD_OUT_DIRECT, 或METHOD_NEITHER。下面的表显示了这些方法和与之对应的能获得输入缓冲与输出缓冲的KIrp中的成员函数：Method Input Buffer Parameter Output Buffer Parameter METHOD_BUFFERED KIrp::IoctlBuffer KIrp::IoctlBuffer METHOD_IN_DIRECT KIrp::IoctlBuffer KIrp::Mdl METHOD_OUT_DIRECT KIrp::IoctlBuffer KIrp::Mdl METHOD_NEITHER KIrp::IoctlType3InputBuffer KIrp::UserBuffer 如果控制代码指明METHOD_BUFFERED，系统分配一个单一的缓冲来作为输入与输出。驱动程序必须在向输出缓冲放数据之前拷贝输入数据。驱动程序通过调用KIrp::IoctlBuffer获得缓冲地址。在完成时，I/O管理器从系统缓冲拷贝数据到提供给Ring 3级调用者使用的缓冲中。驱动程序必须在结束前存储拷贝到IRP的Information成员中的数据个数。如果控制代码不指明METHOD_IN_DIRECT或METHOD_OUT_DIRECT，则DeviceIoControl的参数呈现不同的含义。参数InputBuffer被拷贝到一个系统缓冲，这个缓冲驱动程序可以通过调用KIrp::IoctlBuffer。参数OutputBuffer被映射到KMemory对象，驱动程序对这个对象的访问通过调用KIrp::Mdl来实现。对于METHOD_OUT_DIRECT，调用者必须有对缓冲的写访问权限。注意，对METHOD_NEITHER，内核只提供虚拟地址；它不会做映射来配置缓冲。虚拟地址只对调用进程有效。这里是一个用METHOD_BUFFERED的例子：首先，使用宏CTL_CODE来定义一个IOCTL代码：#define IOCTL_MYDEV_GET_FIRMWARE_REV \CTL_CODE (FILE_DEVICE_UNKNOWN,0,METHOD_BUFFERED,FILE_ANY_ACCESS)现在使用一个DeviceIoControl调用：BOOLEAN b;CHAR FirmwareRev[60];ULONG FirmwareRevSize;b = DeviceIoControl(hDevice, IOCTL_MYDEV_GET_VERSION_STRING, NULL, // no input 注意，这里放的是包含有执行操作命令的字符串指针 0, FirmwareRev, //这里是output串指针，存放从驱动程序中返回的字符串。sizeof(FirmwareRev),& FirmwareRevSize, NULL // not overlapped I/O );如果输出缓冲足够大，设备拷贝串到里面并将拷贝的资结束设置到FirmwareRevSize中。在驱动程序中，代码看起来如下所示：const char* FIRMWARE_REV = "FW 16.33 v5";NTSTATUS MyDevice::DeviceControl( KIrp I ){ ULONG fwLength=0; switch ( I.IoctlCode() ) { case IOCTL_MYDEV_GET_FIRMWARE_REV: fwLength = strlen(FIRMWARE_REV)+1; if (I.IoctlOutputBufferSize() >= fwLength) { strcpy((PCHAR)I.IoctlBuffer(),FIRMWARE_REV); I.Information() = fwLength; return I.Complete(STATUS_SUCCESS); } else { } case . . . } }
上传时间： 2013-10-17
上传用户：gai928943
//芯片资料请到www.elecfans.com查找 //DS1820 C51 子程序//这里以11.0592M晶体为例，不同的晶体速度可能需要调整延时的时间//sbit DQ =P2^1;//根据实际情况定义端口 typedef unsigned char byte;typedef unsigned int word; //延时void delay(word useconds){ for(;useconds>0;useconds--);} //复位byte ow_reset(void){ byte presence; DQ = 0; //pull DQ line low delay(29); // leave it low for 480us DQ = 1; // allow line to return high delay(3); // wait for presence presence = DQ; // get presence signal delay(25); // wait for end of timeslot return(presence); // presence signal returned} // 0=presence, 1 = no part //从 1-wire 总线上读取一个字节byte read_byte(void){ byte i; byte value = 0; for (i=8;i>0;i--) { value>>=1; DQ = 0; // pull DQ low to start timeslot DQ = 1; // then return high delay(1); //for (i=0; i<3; i++); if(DQ)value|=0x80; delay(6); // wait for rest of timeslot } return(value);} //向 1-WIRE 总线上写一个字节void write_byte(char val){ byte i; for (i=8; i>0; i--) // writes byte, one bit at a time { DQ = 0; // pull DQ low to start timeslot DQ = val&0x01; delay(5); // hold value for remainder of timeslot DQ = 1; val=val/2; } delay(5);} //读取温度char Read_Temperature(void){ union{ byte c[2]; int x; }temp; ow_reset(); write_byte(0xCC); // Skip ROM write_byte(0xBE); // Read Scratch Pad temp.c[1]=read_byte(); temp.c[0]=read_byte(); ow_reset(); write_byte(0xCC); //Skip ROM write_byte(0x44); // Start Conversion return temp.x/2;}
上传时间： 2013-11-03
上传用户：hongmo
RS-232-C 是PC 机常用的串行接口,由于信号电平值较高,易损坏接口电路的芯片,与TTL电平不兼容故需使用电平转换电路方能与TTL 电路连接。本产品(转接器),可以实现任意电平下(0.8~15)的UART串行接口到RS-232-C/E接口的无源电平转接, 使用非常方便可靠。 什么是RS-232-C 接口？采用RS-232-C 接口有何特点？传输电缆长度如何考虑？答： 计算机与计算机或计算机与终端之间的数据传送可以采用串行通讯和并行通讯二种方式。由于串行通讯方式具有使用线路少、成本低，特别是在远程传输时，避免了多条线路特性的不一致而被广泛采用。 在串行通讯时，要求通讯双方都采用一个标准接口，使不同 的设备可以方便地连接起来进行通讯。 RS-232-C接口（又称 EIA RS-232-C）是目前最常用的一种串行通讯接口。它是在1970 年由美国电子工业协会（EIA）联合贝尔系统、 调制解调器厂家及计算机终端生产厂家共同制定的用于串行通讯的标准。它的全名是“数据终端设备（DTE）和数据通讯设备（DCE）之间串行二进制数据交换接口技术标准”该标准规定采用一个25 个脚的 DB25 连接器，对连接器的每个引脚的信号内容加以规定，还对各种信号的电平加以规定。(1) 接口的信号内容实际上RS-232-C 的25 条引线中有许多是很少使用的，在计算机与终端通讯中一般只使用3-9 条引线。(2) 接口的电气特性 在RS-232-C 中任何一条信号线的电压均为负逻辑关系。即：逻辑“1”，-5— -15V；逻辑“0” +5— +15V 。噪声容限为2V。即 要求接收器能识别低至+3V 的信号作为逻辑“0”，高到-3V的信号 作为逻辑“1”(3) 接口的物理结构 RS-232-C 接口连接器一般使用型号为DB-25 的25 芯插头座,通常插头在DCE 端,插座在DTE端. 一些设备与PC 机连接的RS-232-C 接口,因为不使用对方的传送控制信号,只需三条接口线,即“发送数据”、“接收数据”和“信号地”。所以采用DB-9 的9 芯插头座，传输线采用屏蔽双绞线。(4) 传输电缆长度由RS-232C 标准规定在码元畸变小于4%的情况下，传输电缆长度应为50 英尺，其实这个4%的码元畸变是很保守的，在实际应用中，约有99%的用户是按码元畸变10-20%的范围工作的，所以实际使用中最大距离会远超过50 英尺，美国DEC 公司曾规定允许码元畸变为10%而得出附表2 的实验结果。其中1 号电缆为屏蔽电缆，型号为DECP.NO.9107723 内有三对双绞线，每对由22# AWG 组成，其外覆以屏蔽网。2 号电缆为不带屏蔽的电缆。 2. 什么是RS-485 接口？它比RS-232-C 接口相比有何特点？答： 由于RS-232-C 接口标准出现较早，难免有不足之处，主要有以下四点：（1） 接口的信号电平值较高，易损坏接口电路的芯片，又因为与TTL 电平不兼容故需使用电平转换电路方能与TTL 电路连接。（2） 传输速率较低，在异步传输时，波特率为20Kbps。（3） 接口使用一根信号线和一根信号返回线而构成共地的传输形式， 这种共地传输容易产生共模干扰，所以抗噪声干扰性弱。（4） 传输距离有限，最大传输距离标准值为50 英尺，实际上也只能 用在50 米左右。针对RS-232-C 的不足，于是就不断出现了一些新的接口标准，RS-485 就是其中之一，它具有以下特点：1. RS-485 的电气特性：逻辑“1”以两线间的电压差为+（2—6） V 表示；逻辑“0”以两线间的电压差为-（2—6）V 表示。接口信号电平比RS-232-C 降低了，就不易损坏接口电路的芯片， 且该电平与TTL 电平兼容，可方便与TTL 电路连接。2. RS-485 的数据最高传输速率为10Mbps3. RS-485 接口是采用平衡驱动器和差分接收器的组合，抗共模干能力增强，即抗噪声干扰性好。4. RS-485 接口的最大传输距离标准值为4000 英尺，实际上可达 3000 米，另外RS-232-C接口在总线上只允许连接1 个收发器， 即单站能力。而RS-485 接口在总线上是允许连接多达128 个收发器。即具有多站能力,这样用户可以利用单一的RS-485 接口方便地建立起设备网络。因RS-485 接口具有良好的抗噪声干扰性，长的传输距离和多站能力等上述优点就使其成为首选的串行接口。 因为RS485 接口组成的半双工网络，一般只需二根连线，所以RS485接口均采用屏蔽双绞线传输。 RS485 接口连接器采用DB-9 的9 芯插头座，与智能终端RS485接口采用DB-9（孔），与键盘连接的键盘接口RS485 采用DB-9（针）。3. 采用RS485 接口时，传输电缆的长度如何考虑？答： 在使用RS485 接口时，对于特定的传输线经，从发生器到负载其数据信号传输所允许的最大电缆长度是数据信号速率的函数，这个 长度数据主要是受信号失真及噪声等影响所限制。下图所示的最大电缆长度与信号速率的关系曲线是使用24AWG 铜芯双绞电话电缆（线 径为0.51mm），线间旁路电容为52.5PF/M，终端负载电阻为100 欧 时所得出。（曲线引自GB11014-89 附录A）。由图中可知，当数据信 号速率降低到90Kbit/S 以下时，假定最大允许的信号损失为6dBV 时， 则电缆长度被限制在1200M。实际上，图中的曲线是很保守的，在实 用时是完全可以取得比它大的电缆长度。 当使用不同线径的电缆。则取得的最大电缆长度是不相同的。例 如：当数据信号速率为600Kbit/S 时，采用24AWG 电缆，由图可知最 大电缆长度是200m，若采用19AWG 电缆（线径为0。91mm）则电缆长 度将可以大于200m； 若采用28AWG 电缆（线径为0。32mm）则电缆 长度只能小于200m。
上传时间： 2013-10-11
上传用户：时代电子小智
PLC TM卡开发系统汇编程序(ATM8051) ;***************** 定义管脚*************************SCL BIT P1.0SDA BIT P1.1GC BIT P1.2BZ BIT P3.6LEDI BIT P1.4LEDII BIT P1.5OK BIT 20H.1OUT1 BIT P1.3OUT2 BIT P1.0OUT3 BIT P1.1RXD BIT P3.0TXD BIT P3.1PCV BIT P3.2WPC BIT P3.3RPC BIT P3.5LEDR BIT P3.4LEDL BIT P3.6TM BIT P3.7;********************定义寄存器***********************ROMDTA EQU 30H;NUMBY EQU 61H;SLA EQU 60H;MTD EQU 2FH;MRD EQU 40H;TEMP EQU 50H;;ORG 00H;;INDEX:MOV P1, #00H;MOV P2, #0FFHMOV MTD ,#00HCALL REEMOV R0,40HCJNE R0,#01,NO;MOV P2,#1CHLJMP VIMEN MOV P2,#79HACALL TOUCHRESET ;JNC NO ;CALL READTM ;CJNE A,#01H,NO;NOPMOV MTD, #00HCALL WEENOPMOV P2,#4AHSETB BZCALL TIMECLR BZMOV PCON, #0FFHVIME:CALL TIME1CALL TOUCHRESETJNC VIMECALL READTMCJNE A, #01H,VIME;NOPNOPNOPIII: MOV MTD,#00HCALL REECALL BBJNB OK,NO1LJMP ZHUNO1:MOV MTD,#10H
上传时间： 2014-03-24
上传用户：448949
中文版详情浏览：http://www.elecfans.com/emb/fpga/20130715324029.html Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications. The UltraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the UltraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation. Some of the UltraScale architecture breakthroughs include: • Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50% • Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability • Potential timing-closure problems and interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization • 3D IC integration makes it possible to build larger devices one process generation ahead of the current industr y standard • Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bandwidth is available within even smaller system power budgets • Greatly enhanced DSP and packet handling The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.
标签： UltraScale Xilinx 架构
上传时间： 2013-11-13
上传用户：瓦力瓦力hong
Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the developmentof designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit theDocumentation in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise,without the prior written consent of Xilinx. Xilinx expressly disclaims any liability arising out of your use of the Documentation. Xilinx reservesthe right, at its sole discretion, to change the Documentation without notice at any time. Xilinx assumes no obligation to correct any errorscontained in the Documentation, or to advise you of any corrections or updates. Xilinx expressly disclaims any liability in connection withtechnical support or assistance that may be provided to you in connection with the Information.
上传时间： 2014-01-13
上传用户：竺羽翎2222
