Log Shifter Gate Level Design using Verilog(IC design Lab) and Lab Note
Log Shifter Gate Level Design using Verilog(IC design Lab) and Lab Note...
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查看全部1631个资源 »PCI设计指南The Xilinx LogiCORE PCI interface is a fully verified, pre-implemented PCI Bus interface. Th
PCI设计指南The Xilinx LogiCORE PCI interface is a fully verified, pre-implemented PCI Bus interface. This interface is available in 32-bit and 64- bit v...
canpie 一个can bus的协议栈 - CAN interface for embedded control - CAN interface for PC (without local
canpie 一个can bus的协议栈 - CAN interface for embedded control - CAN interface for PC (without local processor) - CAN interface for PC (with local...
Intelligent Platform Management Interface Specification Second Generation v2.0
Intelligent Platform Management Interface Specification Second Generation v2.0...
PCI Bus Power Management Interface Specification Revision 1.1
PCI Bus Power Management Interface Specification Revision 1.1...
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