多功能高集成外围器件6. 1 多功能高集成外围器件82371PCI的英文名称：Peripheral Component Interconnect （外围部件互联PCI总线）；82371是PCI总线组件。ISA是：Industry Standard Architecture（工业标准体系结构）IDE是 （Integrated Device Electronics）集成电路设备简称PIIX4PIIX4器件（芯片）的特点1、是一种支持Pentium和PentiumII微处理器的部件。2、82371对ISA桥来说，是一种多功能PCI总线。3、对可移动性和桌面深绿色环境均提供支持。4、电源管理逻辑。5、被集成化的IDE控制器。6、增强了性能的DMA控制器。 （7）基于两个82C59的中断控制器。（8）基于82C54芯片的定时器。（9）USB（Universal Serial Bus）通用串行总线。（10）SMBus系统管理总线。（11）实时时钟（12）顺应Microsoft Win95所需的功能其芯片的逻辑框图如图6-1所示。 PIIX4芯片逻辑框图6.1.1 概述PIIX4芯片是一个多功能的PCI器件，图6-2 是82371在系统中扮演的角色。（续上图）1. PCI与EIO之间的桥（PIIX4芯片）桥是不对程的，是各类不同标准总线与PCI总线连接，82371AB桥也可理解为一种总线转换译码器和控制器，桥内包含复杂的协议总线信号和缓冲器。(1).在PCI系统内，当PIIX4操作时，它总是作为系统内各种模块的主控设备，如USB和DMA控制器、IDE总线和分布式DMA的主控设备等，而且总是以ISA主控设备的名义出现。(2). 在向ISA总线或IDE总线进行传送操作的传送周期期间作为从属设备使用，并对内部寄存器译码。PIIX4芯片（桥）的配置(1).可以把PIIX4芯片配置成整个ISA总线，或ISA总线的子集，也可扩展成EIO总线。在使用EIO总线时，可以把未使用的信号配置成通用的输入和输出。(2).PIIX4可直接驱动5个ISA插槽；(3).能提供字节-交换逻辑、I/O的恢复支持、等待状态的生成以及SYSCLK的生成。(4).提供X-BUS键盘控制器芯片、BIOS芯片、实时时钟芯片、二级微程序器等的选择。2. IDE接口（总线主控设备的权利和同步DMA方式）IDE接口为4个IDE的设备提供支持，比如IDE接口的硬盘和CD-ROM等。注意：目前硬盘接口有5类：IDE、SCSI、Fibre Channel、IEEE1394和USB等。IDE口几乎在PC机最多，因为便宜。SCSI多用于服务器和集群机。IDE的PIO IDE速率：14MB/s；而总线主控设备IDE的速率：33MB/s在PIIX4芯片的IDE系统内，配有两个各次独立的IDE信号通道。3. 具有兼容性的模块—DMA、定时器/计数器、中断控制器等（1）在PIIX4内的两各82C37 DMA控制器经逻辑的组合，产生7个独立的可编程通道。通道[0：3]是通过与8个二进位的硬件连线实现的。通过以字节为单位的计数进行传送。而通道[5：7]是通过16个二进位的连线实现的，以字为单位的计数进行传送。（2）DMA控制器还能通过PCI总线，处理旧的DMA的两个不同的方法提供支持。（3）计数/定时器模块在功能上与82C54等价。（4）中断控制器与ISA兼容，其功能是两个82C59的功能之和。
上传时间： 2013-11-19
上传用户：3到15
The Infineon TriCore provides an Interrupt System with a high safety standard. Thisdocument contains some instructions on how to initiate an Interrupt from an externaldevice. First it will show you how to trigger an Interrupt Service Request by an impulseon Port 0 or Port 1. Then in the second part of the document you can find hints how todebounce impulses to enable the use of a simple switch as input device.Authors: Thomas Bliem, CQ Nguyen / Infineon SMI MD Apps
上传时间： 2013-11-05
上传用户：uuuuuuu
The P90CL301 is a highly integrated 16/32 bit micro-controller especially suitable for applications requiring lowvoltage and low power consumption. It is fully software compatible with the 68000. Furthermore, it provides bothstandard as well as advanced peripheral functions on-chip.One of these peripheral functions is the I2C bus. This report describes worked-out driver software (written in C) toprogram the P90CL301 I2C interface. It also contains interface software routines offering the user a quick start inwriting a complete I2C system application.
上传时间： 2014-01-06
上传用户：气温达上千万的
The 87C576 includes two separate methods of programming theEPROM array, the traditional modified Quick-Pulse method, and anew On-Board Programming technique (OBP).Quick Pulse programming is a method using a number of devicepins in parallel (see Figure 1) and is the traditional way in which87C51 family members have been programmed. The Quick-Pulsemethod supports the following programming functions:– program USER EPROM– verify USER EPROM– program KEY EPROM– program security bits– verify security bits– read signature bytesThe Quick-Pulse method is quite easily suited to standardprogramming equipment as evidenced by the numerous vendors of87C51 compatible programmers on the market today. Onedisadvantage is that this method is not well suited to programming inthe embedded application because of the large number of signallines that must be isolated from the application. In addition, parallelsignals from a programmer would need to be cabled to theapplication’s circuit board, or the application circuit board wouldneed to have logic built-in to perform the programming functions.These requirements have generally made in-circuit programmingusing the modified Quick Pulse method impractical in almost all87C51 family applications.
上传时间： 2013-10-21
上传用户：xiaozhiqban
winCE msdn讲座 XP Embedded Now and the future Windows XP Embedded Developmentand Deployment Model OverviewWindows XP Embedded Component ModelWindows XP Embedded Studio Tools Microsoft WindowsXP Embedded Product Highlights Componentized version of Windows XP Professional~ 12,000 components and updates as of Service Pack 2Flexible localizationSame binaries and API as Windows XP ProfessionalHotfixes and service packsEmbedded Enabling FeaturesRuns on standard PC hardwareSupports boot on hard drives, compact flash, DiskOnChipand read-only mediaSupport for remote install and remote bootHeadless device and remote management supportIntegration with Microsoft management tools
上传时间： 2013-10-31
上传用户：jrsoft
计算机部件要具有通用性，适应不同系统与不同用户的需求，设计必须模块化。计算机部件产品(模块)供应出现多元化。模块之间的联接关系要标准化，使模块具有通用性。模块设计必须基于一种大多数厂商认可的模块联接关系，即一种总线标准。总线的标准总线是一类信号线的集合是模块间传输信息的公共通道，通过它，计算机各部件间可进行各种数据和命令的传送。为使不同供应商的产品间能够互换，给用户更多的选择，总线的技术规范要标准化。总线的标准制定要经周密考虑，要有严格的规定。总线标准（技术规范）包括以下几部分：机械结构规范：模块尺寸、总线插头、总线接插件以及按装尺寸均有统一规定。功能规范：总线每条信号线（引脚的名称）、功能以及工作过程要有统一规定。电气规范：总线每条信号线的有效电平、动态转换时间、负载能力等。总线的发展情况S-100总线：产生于1975年，第一个标准化总线，为微计算机技术发展起到了推动作用。IBM-PC个人计算机采用总线结构（Industry Standard Architecture, ISA)并成为工业化的标准。先后出现8位ISA总线、16位ISA总线以及后来兼容厂商推出的EISA（Extended ISA)32位ISA总线。为了适应微处理器性能的提高及I/O模块更高吞吐率的要求，出现了VL-Bus(VESA Local Bus)和PCI(Peripheral Component Interconnect,PCI）总线。适合小型化要求的PCMCIA(Personal Computer Memory Card International Association)总线，用于笔记本计算机的功能扩展。总线的指标计算机主机性能迅速提高,各功能模块性能也要相应提高,这对总线性能提出更高的要求。总线主要技术指标有几方面：总线宽度：一次操作可以传输的数据位数，如S100为8位，ISA为16位，EISA为32位，PCI-2可达64位。总线宽度不会超过微处理器外部数据总线的宽度。总数工作频率：总线信号中有一个CLK时钟，CLK越高每秒钟传输的数据量越大。ISA、EISA为8MHz，PCI为33.3MHz, PCI-2可达达66.6MHz。单个数据传输周期：不同的传输方式，每个数据传输所用CLK周期数不同。ISA要2个，PCI用1个CLK周期。这决定总线最高数据传输率。5. 总线的分类与层次系统总线：是微处理器芯片对外引线信号的延伸或映射，是微处理器与片外存储器及I/0接口传输信息的通路。系统总线信号按功能可分为三类：地址总线（Where）：指出数据的来源与去向。地址总线的位数决定了存储空间的大小。系统总线：数据总线（What）提供模块间传输数据的路径，数据总线的位数决定微处理器结构的复杂度及总体性能。控制总线（When）：提供系统操作所必需的控制信号，对操作过程进行控制与定时。扩充总线：亦称设备总线，用于系统I/O扩充。与系统总线工作频率不同，经接口电路对系统总统信号缓冲、变换、隔离，进行不同层次的操作（ISA、EISA、MCA)局部总线：扩充总线不能满足高性能设备（图形、视频、网络）接口的要求，在系统总线与扩充总线之间插入一层总线。由于它经桥接器与系统总线直接相连，因此称之为局部总线（PCI）。
上传时间： 2013-11-09
上传用户：nshark
The PL2303 USB to Serial adapter is your smart and convenient accessory forconnecting RS-232 serial devices to your USB-equipped Windows host computer. Itprovides a bridge connection with a standard DB 9-pin male serial port connector inone end and a standard Type-A USB plug connector on the other end. You simplyattach the serial device onto the serial port of the cable and plug the USB connectorinto your PC USB port. It allows a simple and easy way of adding serial connectionsto your PC without having to go thru inserting a serial card and traditional portconfiguration.This USB to Serial adapter is ideal for connecting modems, cellular phones, PDAs,digital cameras, card readers and other serial devices to your computer. It providesserial connections up to 1Mbps of data transfer rate. And since USB does not requireany IRQ resource, more devices can be attached to the system without the previoushassles of device and resource conflicts.Finally, the PL-2303 USB to Serial adapter is a fully USB Specification compliantdevice and therefore supports advanced power management such as suspend andresume operations as well as remote wakeup. The PL-2303 USB Serial cable adapteris designed to work on all Windows operating systems.
上传时间： 2013-11-01
上传用户：ghostparker
The AT89C52 is a low-power, high-performance CMOS 8-bit microcomputer with 8Kbytes of Flash programmable and erasable read only memory (PEROM). The deviceis manufactured using Atmel’s high-density nonvolatile memory technology and iscompatible with the industry-standard 80C51 and 80C52 instruction set and pinout.The on-chip Flash allows the program memory to be reprogrammed in-system or by aconventional nonvolatile memory programmer. By combining a versatile 8-bit CPUwith Flash on a monolithic chip, the Atmel AT89C52 is a powerful microcomputerwhich provides a highly-flexible and cost-effective solution to many embedded controlapplications.
上传时间： 2013-11-10
上传用户：1427796291
中文版详情浏览：http://www.elecfans.com/emb/fpga/20130715324029.html Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications. The UltraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the UltraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation. Some of the UltraScale architecture breakthroughs include: • Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50% • Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability • Potential timing-closure problems and interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization • 3D IC integration makes it possible to build larger devices one process generation ahead of the current industr y standard • Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bandwidth is available within even smaller system power budgets • Greatly enhanced DSP and packet handling The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.
标签： UltraScale Xilinx 架构
上传时间： 2013-11-13
上传用户：瓦力瓦力hong
The standard that governs the design of avioniccomponents and systems, DO-254, is one of the mostpoorly understood but widely applicable standardsin the avionic industry. While information on thegeneral aspects of the standard is easy to obtain, thedetails of exactly how to implement the standard aresketchy. And once an entity develops a process thatachieves compliance, the details of how compliancewas achieved become part of the intellectualproperty of that entity. This white paper focuses onthe details of developing a DO-254 compliantprocess for the design of FPGAs.
上传时间： 2013-11-12
上传用户：q123321
