超声波传感器适用于对大幅的平面进行静止测距。普通的超声波传感器测距范围大概是 2cm~450cm，分辨率3mm（淘宝卖家说的，笔者测试环境没那么好，个人实测比较稳定的 距离10cm~2m 左右，超过此距离就经常有偶然不准确的情况发生了，当然不排除笔者技术 问题。） 测试对象是淘宝上面最便宜的SRF-04 超声波传感器，有四个脚：5v 电源脚（Vcc），触发控制端（Trig），接收端（Echo），地端（GND） 附:SRF 系列超声波传感器参数比较 模块工作原理： 采用IO 触发测距，给至少10us 的高电平信号； 模块自动发送8个40KHz 的方波，自动检测是否有信号返回； 有信号返回，通过IO 输出一高电平，高电平持续的时间就是超声波从发射到返回的时间．测试距离=(高电平时间*声速(340m/s))/2; 电路连接方法 Arduino 程序例子： constintTrigPin = 2; constintEchoPin = 3; floatcm; voidsetup() { Serial.begin(9600); pinMode(TrigPin, OUTPUT); pinMode(EchoPin, INPUT); } voidloop() { digitalWrite(TrigPin, LOW); //低高低电平发一个短时间脉冲去TrigPin delayMicroseconds(2); digitalWrite(TrigPin, HIGH); delayMicroseconds(10); digitalWrite(TrigPin, LOW); cm = pulseIn(EchoPin, HIGH) / 58.0; //将回波时间换算成cm cm = (int(cm * 100.0)) / 100.0; //保留两位小数 Serial.print(cm); Serial.print("cm"); Serial.println(); delay(1000); }
上传时间： 2013-10-18
上传用户：星仔
中文版详情浏览：http://www.elecfans.com/emb/fpga/20130715324029.html Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications. The UltraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the UltraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation. Some of the UltraScale architecture breakthroughs include: • Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50% • Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability • Potential timing-closure problems and interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization • 3D IC integration makes it possible to build larger devices one process generation ahead of the current industr y standard • Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bandwidth is available within even smaller system power budgets • Greatly enhanced DSP and packet handling The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.
标签： UltraScale Xilinx 架构
上传时间： 2013-11-21
上传用户：wxqman
介绍高速电路的设计
标签： High-speed Digital Design 高速数字
上传时间： 2013-12-02
上传用户：wentianyou
Abstract: Designers who must interface 1-Wire temperature sensors with Xilinx field-programmable gate arrays(FPGAs) can use this reference design to drive a DS28EA00 1-Wire slave device. The downloadable softwarementioned in this document can also be used as a starting point to connect other 1-Wire slave devices. The systemimplements a 1-Wire master connected to a UART and outputs temperature to a PC from the DS28EA00 temperaturesensor. In addition, high/low alarm outputs are displayed from the DS28EA00 PIO pins using LEDs.
标签： PicoBlaze Create Master Xilinx
上传时间： 2013-11-12
上传用户：大三三
HDB3(High Density Bipolar三阶高密度双极性)码是在AMI码的基础上改进的一种双极性归零码，它除具有AMI码功率谱中无直流分量，可进行差错自检等优点外，还克服了AMI码当信息中出现连“0”码时定时提取困难的缺点，而且HDB3码频谱能量主要集中在基波频率以下，占用频带较窄，是ITU-TG.703推荐的PCM基群、二次群和三次群的数字传输接口码型,因此HDB3码的编解码就显得极为重要了[1]。目前，HDB3码主要由专用集成电路及相应匹配的外围中小规模集成芯片来实现，但集成程度不高，特别是位同步提取非常复杂，不易实现。随着可编程器件的发展，这一难题得到了很好地解决。
上传时间： 2013-11-01
上传用户：lindor
protel 99se 使用技巧以及常见问题解决方法：里面有一些protel 99se 特别技巧，还有我们经常遇到的一些问题！如何使一条走线至两个不同位置零件的距离相同? 您可先在Design/Rule/High Speed/Matched Net Lengths的规则中来新增规则设定,最后再用Tools/EqualizeNet Lengths 来等长化即可。 Q02、在SCHLIB中造一零件其PIN的属性，如何决定是Passive, Input, I/O, Hi- Z,Power,…..？在HELP中能找到说明吗？市面有关 SIM？PLD？的书吗？或贵公司有讲义？ 你可在零件库自制零件时点选零件Pin脚,并在Electrical Type里,可以自行设定PIN的 属性,您可参考台科大的Protel sch 99se 里面有介绍关于SIM的内容。 Q03、请问各位业界前辈,如何能顺利读取pcad8.6版的线路图,烦请告知 Protel 99SE只能读取P-CAD 2000的ASCII档案格式,所以你必须先将P-CAD8.6版的格式转为P-CAD 2000的档案格式,才能让Protel读取。 Q04、请问我该如何标示线径大小的那个平方呢 你可以将格点大小设小,还有将字形大小缩小,再放置数字的平方位置即可。 Q05、请问我一次如何更改所有组件的字型 您可以点选其中一个组件字型,再用Global的方法就可以达成你的要求。
上传时间： 2015-01-01
上传用户：yxgi5
Introduction to Xilinx Packaging Electronic packages are interconnectable housings for semiconductor devices. The major functions of the electronic packages are to provide electrical interconnections between the IC and the board and to efficiently remove heat generated by the device. Feature sizes are constantly shrinking, resulting in increased number of transistors being packed into the device. Today's submicron technology is also enabling large-scale functional integration and system-on-a-chip solutions. In order to keep pace with these new advancements in silicon technologies, semiconductor packages have also evolved to provide improved device functionality and performance. Feature size at the device level is driving package feature sizes down to the design rules of the early transistors. To meet these demands, electronic packages must be flexible to address high pin counts, reduced pitch and form factor requirements. At the same time,packages must be reliable and cost effective.
上传时间： 2013-11-21
上传用户：不懂夜的黑
This application note describes how to implement the Bus LVDS (BLVDS) interface in the supported Altera ® device families for high-performance multipoint applications. This application note also shows the performance analysis of a multipoint application with the Cyclone III BLVDS example.
标签： Implementing LVDS 522 Bus
上传时间： 2013-10-26
上传用户：苏苏苏苏
Designing withProgrammable Logicin an Analog WorldProgrammable logic devices revolutionizeddigital design over 25 years ago,promising designers a blank chip todesign literally any function and programit in the field. PLDs can be low-logicdensity devices that use nonvolatilesea-of-gates cells called complexprogrammable logic devices (CPLDs)or they can be high-density devicesbased on SRAM look-up tables (LUTs)
标签： Solutions Analog Altera FPGAs
上传时间： 2013-10-27
上传用户：fredguo
Designing withProgrammable Logicin an Analog WorldProgrammable logic devicesrevolutionized digital design over 25years ago, promising designers a blankchip to design literally any functionand program it in the field. PLDs canbe low-logic density devices that usenonvolatile sea-of-gates cells calledcomplex programmable logic devices(CPLDs) or they can be high-densitydevices based on SRAM look-up tables
标签： Solutions Analog Xilinx FPGAs
上传时间： 2013-11-07
上传用户：suicone
