LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY Tone IS PORT ( Index : IN STD_LOGIC_VE…
high+definition 源代码
汇集 high+definition 相关的电路原理图、PCB工程文件、单片机/FPGA源代码、数据手册与应用设计方案。
/* //////////////////////////////////////////////////////////////////////// // // INTEL CORPORATION PROPRIETARY I…
/* //////////////////////////////////////////////////////////////////////// // // INTEL CORPORATION PROPRIETARY I…
// Sched_Conf_Runtime.h,v 1.7 2000/09/22 21:25:42 brunsch Exp // This file was automatically generated by the Scheduler_Factory…
MICRO:EM78P156E OSCILLATOR,RC,Crystal,12,0,1,1 WATCHDOG,Enable,Disable,11,0,1,1 CLOCK,2,4,10,0,0,1 Protect,Enable,Disable,9,0,1…
AVRASM ver. 2.1.0 lcd.asm Thu Aug 30 22:55:35 2007 lcd.asm(939): Including file 'lcd.vec' lcd.asm(940): Including file 'lcd.i…
library ieee; use ieee.std_logic_1164.all; entity tone2 is port( index : in integer range 0 to 15; code :…
library ieee; use ieee.std_logic_1164.all; entity tone2 is port( index : in integer range 0 to 15; code :…
library ieee; use ieee.std_logic_1164.all; entity tone is port( index : in integer range 0 to 15; code : …
1 1 3 # The analysis supports are 2 (low-pass) x 6 (high-pass) -1 0 1 1 -1 0 1 2