A sample program to demonstrate the usage of signal handling in linux C programing language.
标签： demonstrate programing handling language
上传时间： 2013-12-19
上传用户：zhouli
complete information about unix and handling database
标签： information complete handling database
上传时间： 2017-04-16
上传用户：zhaoq123
grievance handling system
上传时间： 2013-12-13
上传用户：wl9454
simple ATmega8 source codes for timer handling
标签： handling ATmega8 simple source
上传时间： 2014-06-20
上传用户：WMC_geophy
simple atmega8 codes for sw and light handling
标签： handling atmega8 simple codes
上传时间： 2013-12-16
上传用户：1109003457
handling IRPs: What Every Driver Writer Needs to Know
标签： handling Driver Writer Every
上传时间： 2014-01-22
上传用户：541657925
handling Request Parameters with Form Beans
标签： Parameters handling Request Beans
上传时间： 2013-12-29
上传用户：LouieWu
介绍基于ISA总线与KH-9300的数据采集板卡的设置，详细说明8254定时计数器及8259中断控制器的结构特点、工作方式、控制字等，探讨中断类型、中断处理程序、中断矢量表及其填写。重点讲述使用TorboC编写中断服务程序的方法，应注意的主要问题及程序测试的结果。 Abstract: The settings of KH-9300 data acquisition board based on the ISA bus is introduced,the structural characteristics,working methods,control characters of the timing counter 8254 and interruptioncontroller 8259 are explained in detail.The interruption type,interrupt handling programs,interruption vector table and its filling also are discussed.Further,great emphasis is put on the method of interrupt service program compiled by Torbo C,the main issues that should be noted,and the results of program testing.
上传时间： 2013-11-14
上传用户：qq527891923
This application note shows how to write an Inter Integrated Circuit bus driver (I²C) for the Philips P90CL301micro-controller.It is not only an example of writing a driver, but it also includes a set of application interface software routines toquickly implement a complete I²C multi-master system application.For specific applications the user will have to make minimal changes in the driver program. Using the drivermeans linking modules to your application software and including a header-file into the application sourceprograms. A small example program of how to use the driver is listed.The driver supports i.a. polled or interrupt driven message handling, slave message transfers and multi-mastersystem applications. Furthermore, it is made suitable for use in conjunction with real time operating systems, likepSOS+.
上传时间： 2013-11-23
上传用户：weixiao99
中文版详情浏览：http://www.elecfans.com/emb/fpga/20130715324029.html Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications. The UltraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the UltraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation. Some of the UltraScale architecture breakthroughs include: • Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50% • Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability • Potential timing-closure problems and interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization • 3D IC integration makes it possible to build larger devices one process generation ahead of the current industr y standard • Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bandwidth is available within even smaller system power budgets • Greatly enhanced DSP and packet handling The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.
标签： UltraScale Xilinx 架构
上传时间： 2013-11-13
上传用户：瓦力瓦力hong
