DDS divider clock AHDL
DDS divider clock AHDL...
DDS divider clock AHDL...
multiplier and divider verilog codes...
this file is divider vhdl program...
a divider design based on verilog language...
program to perform sequential divider in vhdl...
实现分频,低通1khz 中1到5khz,高5到20khz...
It is n-bit sequential divider in verilog language...
Frequency Modulation...
frequency multiplier...
Time-Frequency Toolbox,其中包含一些常用的matlab程序,很好用的...