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VHDL/FPGA/Verilog Three-input Majority Voter -- The entity declaration is followed by three alternative architectures
Three-input Majority Voter
-- The entity declaration is followed by three alternative architectures which achieve the same functionality in different ways.
单片机开发 Swfdec still is development software, but has also followed a rigid no-crashes-allowed policy. I b
Swfdec still is development software, but has also followed a rigid
no-crashes-allowed policy. I believe it s stable enough now to be
installed as a default plugin for people that can live with occasional
crashes of their browser. But don t blame me if it does crash. File a
bug at https://bugs.f ...
matlab例程 PRINCIPLE: Removal of the row mean from each row, followed by division of the row by the respective
PRINCIPLE: Removal of the row mean from each row, followed by division of the row by the respective row standard deviation.
系统设计方案 JPEG Image compression using IJG standards followed
JPEG Image compression using IJG standards followed
allegro Verilog Coding Style for Efficient Digital Design
 
In this paper, we discuss efficient coding and design styles using verilog. This can beimmensely helpful for any digital designer initiating designs. Here, we address different problems rangingfrom RTL-Gate Level simulation mismatch to race conditions in writing behavioral models. All the ...
电源技术 降压升压型控制器简化手持式产品的DC/DC转换器设计
 
A number of conventional solutions have been available forthe design of a DC/DC converter where the output voltageis within the input voltage range—a common scenarioin Li-Ion battery-powered applications—but none werevery attractive until now. Conventional topologies, suchas S ...
教程资料 XAPP122 - Spartan-XL FPGA的Express配置
Express Mode uses an 8-bit wide bus path for fast configuration of Xilinx FPGAs. Thisapplication note provides information on how to perform Express configuration specifically forthe Spartan™-XL family. The Express mode signals and their associated timing are defined.The steps of Express con ...
教程资料 ZBT SRAM控制器参考设计,xilinx提供VHDL代码
ZBT SRAM控制器参考设计,xilinx提供VHDL代码
Description:
  Contains the following files
    readme.txt appnote_zbtp.vhd appnote_zbtf.vhd appnote_zbt.ucf
Platform:
  All
Installation/Use:
  Use 'unzip' on the .zip file and 'gunzip' followed by & ...
通信网络 HITECH与电脑的通信协议
1 Communication Protocol (Computer as master)
 
The communication protocol describes here allows your computer to access 4096 internal registers (W0000-W4095) and 1024 internal relays&n ...
可编程逻辑 XAPP122 - Spartan-XL FPGA的Express配置
Express Mode uses an 8-bit wide bus path for fast configuration of Xilinx FPGAs. Thisapplication note provides information on how to perform Express configuration specifically forthe Spartan™-XL family. The Express mode signals and their associated timing are defined.The steps of Express con ...