fifos
共 15 篇文章
fifos 相关的电子技术资料，包括技术文档、应用笔记、电路设计、代码示例等，共 15 篇文章，持续更新中。
利用FIFOs实现USB与DSP的高速数据传输
· 摘要： 利用两片SN74V245实现了TMS320C6201与EZ-USB FX2LP系列芯片CY7C68013A的连接,介绍了TMS320C6201的外部存储接口(EMIF)和CY7C68013A的通用可编程接口(GPIF)以及它们与SN74V245的连接方案,深入研究了GPIF的波形描述符编写和固件程序开发.
用CY7C436xx系列同步FIFO进行设计
Cypress Semiconductor offers four families of 3.3V x36<BR>FIFOs: The unidirectional with Bus Matchin
对CY7B923 CY7B933(HOTLink)与具有宽带数据总线、时钟控制的FIFOs接口的介绍
This application note describes a reframe controller for the<BR>Cypress CY7B933 HOTLink™ Recei
对CY7B923 CY7B933(HOTLink)与时钟控制的FIFOs接口的介绍
This application note describes the behavior of the RDY<BR>(Ready) pin in several modes of operation
用XC3000系列配置基于寄存器的同 异步FIFO存储器
In the absence of RAM, XC3000 FIFOs must be constructed<BR>with registers. Using both flip-flops, on
介绍大型Cypress公司FIFO器件的内部工作和如何应用这些器件进行深度和宽度的扩展
This application note explains the internal operation of the large FIFOs manufactured by Cypress and
利用FIFOs 实现USB 与DSP 的高速数据传输
利用两片SN74V245实现了TMS320C6201与EZ-USB FX2LP系列芯片CY7C68013A的<BR>连接，介绍了TMS320C6201的外部存储接口（EMIF）和CY7C68013A的
用XC3000系列配置基于寄存器的同 异步FIFO存储器
In the absence of RAM, XC3000 FIFOs must be constructed<BR>with registers. Using both flip-flops, on
si4463完整DEMO板原理图PCB
SILABS新推出EZradioPRO系列RFIC:SI4463完整DEMO板的开发包下载.
里面压缩了4个文件。PCB图、原理图、DEMO代码。
PCB图、原理图、DEMO程序 ,适合长远距离的无线数据传输应用.其发射功率+20dbm,接收灵敏度-116dbm,通讯距离2000米.
SI4463-B1-FMR特点
频率范围= 119–1050 MHz
接收灵敏度 = –126 dBm
A badic controller for the UART. It incorporates a -- transmit and receive FIFO (fr
A badic controller for the UART. It incorporates a
-- transmit and receive FIFO (from Max+Plus II s MegaWizard
-- plug-in manager). Note that no checking is done to s
这个设计是使用Virtex-4实现DDR的控制器的
这个设计是使用Virtex-4实现DDR的控制器的，设计分为三个主要模块：Front-End FIFOs,DDR SDRAM Controller和Datapath Module。其中主要是DDR SDRAM Controller,当然还有测试模块。
Enhanced version of the Serial Peripheral Interface available on Motorola s MC68HC11 family of CPUs.
Enhanced version of the Serial Peripheral Interface available on Motorola s MC68HC11 family of CPUs.Enhancements include a wider supported operating frequency range, 4deep read and write fifos, and pr
This paper will discuss the design of an asynchronous FIFO,Asynchronous FIFOs are widely used in the
This paper will discuss the design of an asynchronous FIFO,Asynchronous FIFOs are widely used in the computer networking industry to receive data at
a particular frequency and transmit them at anothe
The first task at hand is to set up the endpoints appropriately for this example. The following code
The first task at hand is to set up the endpoints appropriately for this example. The following code switches the CPU clock speed
to 48 MHz (since at power-on default it is 12 MHz), and sets up EP2 a
XAPP807-封装最小的三态以太网MAC处理引擎
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The Tri-Mode Ethernet MAC (TEMAC) UltraController-II module is a minimal footprint,embedded network processing engine based on the PowerPC™ 405 (PPC405) processor coreand the TEMAC core e