PCI express是由Intel，Dell，Compaq，IBM，Microsoft等PCI SIG联合成立的Arapahoe Work Group共同草拟并推举成取代PCI总线标准的下一代标准。PCI express利用串行的连接特点能轻松将数据传输速度提到一个很高的频率，达到远远超出PCI总线的传输速率。一个PCI express连接可以被配置成x1，x2，x4，x8，x12，x16和x32的数据带宽。x1的通道能实现单向312.5 MB／s（2.5 Gb／s）的传输速率。Xilinx公司的Virtex5系列FPGA芯片内嵌PCI-expressEndpoint Block硬核，为实现单片可配置PCI-express总线解决方案提供了可能。 本文在研究PCI-express接口协议和PCI-express Endpoint Block硬核的基础上，使用Virtex5LXT50 FPGA芯片设计PCI express接口硬件电路，实现PCI-express数据传输
上传时间： 2013-12-26
上传用户：wtrl
PCI express 协议由于其高速串行、系统拓扑简单等特点被广泛用于各种领域。Altera公司的Arria II GX FPGA内集成了支持链式DMA传输功能的PCI express硬核，适应了PCI express总线高速度的要求。文中利用Jungo公司的WinDriver软件实现了链式DMA的上层应用设计。首先给出了链式DMA实现的基本过程，接着分析了链式DMA数据传输需要处理的几个问题，给出了相应的解决办法和策略。采用这些方法，保证了DAM数据传输的正确性，简化了底层FPGA应用逻辑的设计。
上传时间： 2014-12-21
上传用户：squershop
白皮书：采用低成本FPGA实现高效的低功耗PCIe接口 了解一个基于DDR3存储器控制器的真实PCI express® （PCIe®） Gen1x4参考设计演示高效的Cyclone V FPGA怎样降低系统总成本，同时实现性能和功耗目标。点击马上下载！
上传时间： 2013-10-17
上传用户：康郎
PCIe规范，光纤通道控制器
上传时间： 2013-10-21
上传用户：ppeyou
FPGA 设计不再像过去一样只是作为“胶连逻辑 (Gluelogic)”了，由于其复杂度逐年增加，通常还会集成极富挑战性的 IP 核，如 PCI express® 核等。新型设计中的复杂模块即便不作任何改变也会在满足 QoR(qualityof-result) 要求方面遇到一些困难。保留这些模块的时序非常耗时，既让人感到头疼，往往还徒劳无功。设计保存流程可以帮助客户解决这一难题，既可以让他们满足设计中关键模块的时序要求，又能在今后重用实现的结果，从而显著减少时序收敛过程中的运行次数。
上传时间： 2013-11-19
上传用户：invtnewer
采用Xlinx公司的Virtex5系列FPGA设计了一个用于多种高速串行协议的数据交换模块,并解决了该模块实现中的关键问题.该交换模块实现4X模式RapidIO协议与4X模式PCI express协议之间的数据交换,以及自定义光纤协议与4X模式PCI express协议之间的数据交换,实现了单字读写以及DMA操作,并提供高速稳定的传输带宽.
上传时间： 2013-10-19
上传用户：angle
The LogiCORE™ GTP Wizard automates the task of creating HDL wrappers to configure the high-speed serial GTP transceivers in Virtex™-5 LXT and SXT devices. The menu-driven interface allows one or more GTP transceivers to be configured using pre-definedtemplates for popular industry standards, or from scratch, to support a wide variety of custom protocols.The Wizard produces a wrapper, an example design, and a testbench for rapid integration and verification of the serial interface with your custom function Features• Creates customized HDL wrappers to configureVirtex-5 RocketIO™ GTP transceivers• Users can configure Virtex-5 GTP transceivers toconform to industry standard protocols usingpredefined templates, or tailor the templates forcustom protocols• Included protocol templates provide support for thefollowing specifications: Aurora, CPRI, FibreChannel 1x, Gigabit Ethernet, HD-SDI, OBSAI,OC3, OC12, OC48, PCI express® (PCIe®), SATA,SATA II, and XAUI• Automatically configures analog settings• Each custom wrapper includes example design, testbench; and both implementation and simulation scripts
标签： Transceiver Virtex Wizar GTP
上传时间： 2013-10-20
上传用户：dave520l
UG341 - LogiCORE™ Endpoint Block Plus v1.6 for PCI express® 用户指南
标签： LogiCORE Endpoint Block 341
上传时间： 2013-10-16
上传用户：jeffery
This document provides practical, common guidelines for incorporating PCI express interconnect layouts onto Printed Circuit Boards (PCB) ranging from 4-layer desktop baseboard designs to 10- layer or more server baseboard designs. Guidelines and constraints in this document are intended for use on both baseboard and add-in card PCB designs. This includes interconnects between PCI express devices located on the same baseboard (chip-to-chip routing) and interconnects between a PCI express device located “down” on the baseboard and a device located “up” on an add-in card attached through a connector. This document is intended to cover all major components of the physical interconnect including design guidelines for the PCB traces, vias and AC coupling capacitors, as well as add-in card edge-finger and connector considerations. The intent of the guidelines and examples is to help ensure that good high-speed signal design practices are used and that the timing/jitter and loss/attenuation budgets can also be met from end-to-end across the PCI express interconnect. However, while general physical guidelines and suggestions are given, they may not necessarily guarantee adequate performance of the interconnect for all layouts and implementations. Therefore, designers should consider modeling and simulation of the interconnect in order to ensure compliance to all applicable specifications. The document is composed of two main sections. The first section provides an overview of general topology and interconnect guidelines. The second section concentrates on physical layout constraints where bulleted items at the beginning of a topic highlight important constraints, while the narrative that follows offers additional insight.
上传时间： 2014-01-23
上传用户：s363994250
The power of programmability gives industrial automation designers a highly efficient， cost-effective alternative to traditional motor control units （MCUs）。 The parallel-processing power， fast computational speeds， and connectivity versatility of Xilinx® FPGAs can accelerate the implementation of advanced motor control algorithms such as Field Oriented Control （FOC）。 Additionally， Xilinx devices lower costs with greater on-chip integration of system components and shorten latencies with high-performance digital signal processing （DSP） that can tackle compute-intensive functions such as PID Controller， Clark/Park transforms， and Space Vector PWM. The Xilinx Spartan®-6 FPGA Motor Control Development Kit gives designers an ideal starting point for evaluating time-saving， proven， motor-control reference designs. The kit also shortens the process of developing custom control capabilities， with integrated peripheral functions （Ethernet， PowerLink， and PCI® express）， a motor-control FPGA mezzanine card （FMC） with built-in Texas Instruments motor drivers and high-precision Delta-Sigma modulators， and prototyping support for evaluating alternative front-end circuitry.
上传时间： 2013-10-28
上传用户：wujijunshi
