虫虫首页| 资源下载| 资源专辑| 精品软件
登录| 注册

end-to-en-delay

  • An easy way to work with Exter

    Internal Interrupts are used to respond to asynchronous requests from a certain part of themicrocontroller that needs to be serviced. Each peripheral in the TriCore as well as theBus Control Unit, the Debug Unit, the Peripheral Control Processor (PCP) and the CPUitself can generate an Interrupt Request.So what is an external Interrupt?An external Interrupt is something alike as the internal Interrupt. The difference is that anexternal Interrupt request is caused by an external event. Normally this would be a pulseon Port0 or Port1, but it can be even a signal from the input buffer of the SSC, indicatingthat a service is requested.The User’s Manual does not explain this aspect in detail so this ApNote will explain themost common form of an external Interrupt request. This ApNote will show that there is aneasy way to react on a pulse on Port0 or Port1 and to create with this impulse an InterruptService Request. Later in the second part of the document, you can find hints on how todebounce impulses to enable the use of a simple switch as the input device.Note: You will find additional information on how to setup the Interrupt System in theApNote “First steps through the TriCore Interrupt System” (AP3222xx)1. It would gobeyond the scope of this document to explain this here, but you will find selfexplanatoryexamples later on.

    标签: Exter easy work with

    上传时间: 2013-10-27

    上传用户:zhangyigenius

  • Using the 87LPC76X microcontro

    I2C interface, is a very powerful tool for system designers. Theintegrated protocols allow systems to be completely software defined.Software development time of different products can be reduced byassembling a library of reusable software modules. In addition, themultimaster capability allows rapid testing and alignment ofend-products via external connections to an assembly-line computer.The mask programmable 87LPC76X and its EPROM version, the87LPC76X, can operate as a master or a slave device on the I2Csmall area network. In addition to the efficient interface to thededicated function ICs in the I2C family, the on-board interfacefacilities I/O and RAM expansion, access to EEPROM andprocessor-to-processor communications.

    标签: microcontro Using 76X LPC

    上传时间: 2013-12-30

    上传用户:Artemis

  • PIC单片机程序设计基础

    1、程序的基本格式先介绍二条伪指令:EQU ——标号赋值伪指令ORG ——地址定义伪指令PIC16C5X在RESET后指令计算器PC被置为全“1”,所以PIC16C5X几种型号芯片的复位地址为:PIC16C54/55:1FFHPIC16C56:3FFHPIC16C57/58:7FFH一般来说,PIC的源程序并没有要求统一的格式,大家可以根据自己的风格来编写。但这里我们推荐一种清晰明了的格式TITLE This is ⋯⋯ ;程序标题;--------------------------------------;名称定义和变量定义;--------------------------------------F0 EQU 0RTCC EQU 1PC EQU 2STATUS EQU 3FSR EQU 4RA EQU 5RB EQU 6RC EQU 7┋PIC16C54 EQU 1FFH ;芯片复位地址PIC16C56 EQU 3FFHPIC16C57 EQU 7FFH;-----------------------------------------ORG PIC16C54 GOTO MAIN ;在复位地址处转入主程序ORG 0 ;在0000H开始存放程序;-----------------------------------------;子程序区;-----------------------------------------DELAY MOVLW 255┋RETLW 0;------------------------------------------;主程序区;------------------------------------------MAINMOVLW B‘00000000’TRIS RB ;RB已由伪指令定义为6,即B口┋LOOPBSF RB,7 CALL DELAYBCF RB,7 CALL DELAY┋GOTO LOOP;-------------------------------------------END ;程序结束注:MAIN标号一定要处在0页面内。2、程序设计基础

    标签: PIC 单片机程序设计

    上传时间: 2013-11-14

    上传用户:cjf0304

  • 3.3v看门狗芯片

    The STWD100 watchdog timer circuits are self-contained devices which prevent systemfailures that are caused by certain types of hardware errors (non-responding peripherals,bus contention, etc.) or software errors (bad code jump, code stuck in loop, etc.).The STWD100 watchdog timer has an input, WDI, and an output, WDO (see Figure 2). Theinput is used to clear the internal watchdog timer periodically within the specified timeoutperiod, twd (see Section 3: Watchdog timing). While the system is operating correctly, itperiodically toggles the watchdog input, WDI. If the system fails, the watchdog timer is notreset, a system alert is generated and the watchdog output, WDO, is asserted (seeSection 3: Watchdog timing).The STWD100 circuit also has an enable pin, EN (see Figure 2), which can enable ordisable the watchdog functionality. The EN pin is connected to the internal pull-downresistor. The device is enabled if the EN pin is left floating.

    标签: 3.3 看门狗 芯片

    上传时间: 2013-10-22

    上传用户:taiyang250072

  • 51汇编程序实例

    51汇编程序实例:举一例说明:流水灯加数码管 LOOP:     ; 标号CLR P2.6   ;选中p2.6 数码管左边的8字使能SETB P2.7   ;p2.7不使能。 右边的数码管消隐MOV P0,#28H  ;把28h送p0口;数码管显示 0LCALL DELAY ;延时MOV P0,#0FFH   ;0ffh 送p0口,数码管清除CLR P1.0    ;点亮p1.0发光管MOV P0,#7EH ;把7eh送p0口;数码管显示 1LCALL DELAYMOV P0,#0FFHCLR P1.1      ;点亮p1.0发光管CLR P1.0      ;点亮p1.0发光管MOV P0,#0A2H   ;数码管显示 2LCALL DELAYMOV P0,#0FFHCLR P1.2CLR P1.1CLR P1.0MOV P0,#62H    ;数码管显示 3LCALL DELAYMOV P0,#0FFHCLR P1.3CLR P1.2CLR P1.1CLR P1.0MOV P0,#74H    ;数码管显示 4LCALL DELAYMOV P0,#0FFHCLR P1.4CLR P1.3CLR P1.2CLR P1.1CLR P1.0MOV P0,#61H   ;数码管显示 5;LCALL DELAYMOV P0,#0FFHCLR P1.5CLR P1.4CLR P1.3CLR P1.2CLR P1.1CLR P1.0MOV P0,#21H     ; 数码管显示 6LCALL DELAYMOV P0,#0FFHCLR P1.6CLR P1.5CLR P1.4CLR P1.3CLR P1.2CLR P1.1CLR P1.0MOV P0,#7AH   ; 数码管显示 7LCALL DELAYMOV P0,#0FFHCLR P1.7CLR P1.6CLR P1.5CLR P1.4CLR P1.3CLR P1.2CLR P1.1CLR P1.0MOV P0,#20H   ; 数码管显示 8LCALL DELAYMOV P0,#0FFHLCALL DELAYMOV P0,#0FFHMOV P1,#0FFH;程序到此结果为左边的数码管显示0,1,2,3,4,5,6,7,8;p1.0------------p1.7指示灯依次点亮SETB P2.6   ; 左边的8消隐CLR P2.7   ;选中p2.7 数码管右边的8字使能 ,;MOV P0,#28HLCALL DELAYMOV P0,#0FFHMOV P1,#0FFHCLR P1.0MOV P0,#7EHLCALL DELAYMOV P0,#0FFHMOV P1,#0FFHCLR P1.1MOV P0,#0A2HLCALL DELAYMOV P0,#0FFHMOV P1,#0FFHCLR P1.2MOV P0,#62HLCALL DELAYMOV P0,#0FFHMOV P1,#0FFHCLR P1.3MOV P0,#74HLCALL DELAYMOV P0,#0FFHMOV P1,#0FFHCLR P1.4MOV P0,#61HLCALL DELAYMOV P0,#0FFHMOV P1,#0FFHCLR P1.5MOV P0,#21HLCALL DELAYMOV P0,#0FFHMOV P1,#0FFHCLR P1.6MOV P0,#7AHLCALL DELAYMOV P0,#0FFHMOV P1,#0FFHCLR P1.7MOV P0,#20HLCALL DELAYMOV P0,#0FFHMOV P1,#0FFHMOV P0,#0FFHMOV P1,#0FFH;这一段和上一段基本相同, 不同的是右边的数码管依次显示012345678,左边的不亮;;同时p1口的灯流动显示:AJMP LOOP; 注意: 程序运行到此跳转到开始标号,重复执行:DELAY:  ;延时子程序;参考前面的教程:CLR P3.3  ;注意小喇叭在3.3口, 这里可以使小喇叭发出嗒,嗒声MOV  R7,#255NOPNOPD1:MOV R6,#255setb p3.3D2: DJNZ R6,D2clr p3.3DJNZ R7,D1SETB P3.3RETENDLOOP:                ; 标号CLR P2.6             ;选中p2.6 数码管左边的8字使能SETB P2.7            ;p2.7不使能。 右边的数码管消隐MOV P0,#28H          ;把28h送p0口;数码管显示 0    ;28为1010000LCALL DELAY          ;  延时程序MOV P0,#0FFH         ;0ffh 送p0口,数码管清除;P0口为11111111CLR P1.0             ;点亮p1.0发光管; P1。0为电平,P0口为11111110MOV P0,#7EH          ;把7eh送p0口;数码管显示 1; P1。0为低电平,P0口为11111110LCALL DELAY          ;  延时程序MOV P0,#0FFHMOV P0,#0FFH         ;0ffh 送p0口,数码管清除;P0口为11111111 清一次显示这条是清显示的

    标签: 汇编 程序实例

    上传时间: 2013-10-31

    上传用户:gundamwzc

  • DSP从入门到精通全集EN

    DSP从入门到精通全集EN

    标签: DSP

    上传时间: 2013-11-04

    上传用户:caiqinlin

  • Xilinx UltraScale:新一代架构满足您的新一代架构需求(EN)

      中文版详情浏览:http://www.elecfans.com/emb/fpga/20130715324029.html   Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture    The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications.   The UltraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the UltraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation.   Some of the UltraScale architecture breakthroughs include:   • Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50%    • Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability   • Potential timing-closure problems and interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization   • 3D IC integration makes it possible to build larger devices one process generation ahead of the current industr y standard    • Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bandwidth is available within even smaller system power budgets   • Greatly enhanced DSP and packet handling   The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.

    标签: UltraScale Xilinx 架构

    上传时间: 2013-11-13

    上传用户:瓦力瓦力hong

  • 采用TÜV认证的FPGA开发功能安全系统

    This white paper discusses how market trends, the need for increased productivity, and new legislation have accelerated the use of safety systems in industrial machinery. This TÜV-qualified FPGA design methodology is changing the paradigms of safety designs and will greatly reduce development effort, system complexity, and time to market. This allows FPGA users to design their own customized safety controllers and provides a significant competitive advantage over traditional microcontroller or ASIC-based designs. Introduction The basic motivation of deploying functional safety systems is to ensure safe operation as well as safe behavior in cases of failure. Examples of functional safety systems include train brakes, proximity sensors for hazardous areas around machines such as fast-moving robots, and distributed control systems in process automation equipment such as those used in petrochemical plants. The International Electrotechnical Commission’s standard, IEC 61508: “Functional safety of electrical/electronic/programmable electronic safety-related systems,” is understood as the standard for designing safety systems for electrical, electronic, and programmable electronic (E/E/PE) equipment. This standard was developed in the mid-1980s and has been revised several times to cover the technical advances in various industries. In addition, derivative standards have been developed for specific markets and applications that prescribe the particular requirements on functional safety systems in these industry applications. Example applications include process automation (IEC 61511), machine automation (IEC 62061), transportation (railway EN 50128), medical (IEC 62304), automotive (ISO 26262), power generation, distribution, and transportation. 图Figure 1. Local Safety System

    标签: FPGA 安全系统

    上传时间: 2013-11-05

    上传用户:维子哥哥

  • tcp ip协议详解 中文版PDF

    很多不同的厂家生产各种型号的计算机,它们运行完全不同的操作系统,但TCP.IP协议族允许它们互相进行通信。这一点很让人感到吃惊,因为它的作用已远远超出了起初的设想。T C P / I P起源于6 0年代末美国政府资助的一个分组交换网络研究项目,到9 0年代已发展成为计算机之间最常应用的组网形式。它是一个真正的开放系统,因为协议族的定义及其多种实现可以不用花钱或花很少的钱就可以公开地得到。它成为被称作“全球互联网”或“因特网(Internet)”的基础,该广域网(WA N)已包含超过1 0 0万台遍布世界各地的计算机。本章主要对T C P / I P协议族进行概述,其目的是为本书其余章节提供充分的背景知识。 TCP.IP协议 缩略语 ACK (ACKnowledgment) TCP首部中的确认标志 API (Application Programming Interface) 应用编程接口 ARP (Address Resolution Protocol) 地址解析协议 ARPANET(Defense Advanced Research Project Agency NETwork) (美国)国防部远景研究规划局 AS (Autonomous System) 自治系统 ASCII (American Standard Code for Information Interchange) 美国信息交换标准码 ASN.1 (Abstract Syntax Notation One) 抽象语法记法1 BER (Basic Encoding Rule) 基本编码规则 BGP (Border Gateway Protocol) 边界网关协议 BIND (Berkeley Internet Name Domain) 伯克利I n t e r n e t域名 BOOTP (BOOTstrap Protocol) 引导程序协议 BPF (BSD Packet Filter) BSD 分组过滤器 CIDR (Classless InterDomain Routing) 无类型域间选路 CIX (Commercial Internet Exchange) 商业互联网交换 CLNP (ConnectionLess Network Protocol) 无连接网络协议 CRC (Cyclic Redundancy Check) 循环冗余检验 CSLIP (Compressed SLIP) 压缩的S L I P CSMA (Carrier Sense Multiple Access) 载波侦听多路存取 DCE (Data Circuit-terminating Equipment) 数据电路端接设备 DDN (Defense Data Network) 国防数据网 DF (Don’t Fragment) IP首部中的不分片标志 DHCP (Dynamic Host Configuration Protocol) 动态主机配置协议 DLPI (Data Link Provider Interface) 数据链路提供者接口 DNS (Domain Name System) 域名系统 DSAP (Destination Service Access Point) 目的服务访问点 DSLAM (DSL Access Multiplexer) 数字用户线接入复用器 DSSS (Direct Sequence Spread Spectrum) 直接序列扩频 DTS (Distributed Time Service) 分布式时间服务 DVMRP (Distance Vector Multicast Routing Protocol) 距离向量多播选路协议 EBONE (European IP BackbONE) 欧洲I P主干网 EOL (End of Option List) 选项清单结束 EGP (External Gateway Protocol) 外部网关协议 EIA (Electronic Industries Association) 美国电子工业协会 FCS (Frame Check Sequence) 帧检验序列 FDDI (Fiber Distributed Data Interface) 光纤分布式数据接口 FIFO (First In, First Out) 先进先出 FIN (FINish) TCP首部中的结束标志 FQDN (Full Qualified Domain Name) 完全合格的域名 FTP (File Transfer Protocol) 文件传送协议 HDLC (High-level Data Link Control) 高级数据链路控制 HELLO 选路协议 IAB (Internet Architecture Board) Internet体系结构委员会 IANA (Internet Assigned Numbers Authority) Internet号分配机构 ICMP (Internet Control Message Protocol) Internet控制报文协议 IDRP (InterDomain Routing Protocol) 域间选路协议 IEEE (Institute of Electrical and Electronics Engineering) (美国)电气与电子工程师协会 IEN (Internet Experiment Notes) 互联网试验注释 IESG (Internet Engineering Steering Group) Internet工程指导小组 IETF (Internet Engineering Task Force) Internet工程专门小组 IGMP (Internet Group Management Protocol) Internet组管理协议 IGP (Interior Gateway Protocol) 内部网关协议 IMAP (Internet Message Access Protocol) Internet报文存取协议 IP (Internet Protocol) 网际协议 I RTF (Internet Research Task Force) Internet研究专门小组 IS-IS (Intermediate System to Intermediate System Protocol) 中间系统到中间系统协议 ISN (Initial Sequence Number) 初始序号 ISO (International Organization for Standardization) 国际标准化组织 ISOC (Internet SOCiety) Internet协会 LAN (Local Area Network) 局域网 LBX (Low Bandwidth X) 低带宽X LCP (Link Control Protocol) 链路控制协议 LFN (Long Fat Net) 长肥网络 LIFO (Last In, First Out) 后进先出 LLC (Logical Link Control) 逻辑链路控制 LSRR (Loose Source and Record Route) 宽松的源站及记录路由 MBONE (Multicast Backbone On the InterNEt) Internet上的多播主干网 MIB (Management Information Base) 管理信息库 MILNET (MILitary NETwork) 军用网 MIME (Multipurpose Internet Mail Extensions) 通用I n t e r n e t邮件扩充 MSL (Maximum Segment Lifetime) 报文段最大生存时间 MSS (Maximum Segment Size) 最大报文段长度 M TA (Message Transfer Agent) 报文传送代理 MTU (Maximum Transmission Unit) 最大传输单元 NCP (Network Control Protocol) 网络控制协议 NFS (Network File System) 网络文件系统 NIC (Network Information Center) 网络信息中心 NIT (Network Interface Tap) 网络接口栓(S u n公司的一个程序) NNTP (Network News Transfer Protocol) 网络新闻传送协议 NOAO (National Optical Astronomy Observatories) 国家光学天文台 NOP (No Operation) 无操作 NSFNET (National Science Foundation NETwork) 国家科学基金网络 NSI (NASA Science Internet) (美国)国家宇航局I n t e r n e t NTP (Network Time Protocol) 网络时间协议 NVT (Network Virtual Terminal) 网络虚拟终端 OSF (Open Software Foudation) 开放软件基金 OSI (Open Systems Interconnection) 开放系统互连 OSPF (Open Shortest Path First) 开放最短通路优先 PAWS (Protection Against Wrapped Sequence number) 防止回绕的序号 PDU (Protocol Data Unit) 协议数据单元 POSIX (Portable Operating System Interface) 可移植操作系统接口 PPP (Point-to-Point Protocol) 点对点协议 PSH (PuSH) TCP首部中的急迫标志 RARP (Reverse Address Resolution Protocol) 逆地址解析协议 RFC (Request For Comments) Internet的文档,其中的少部分成为标准文档 RIP (Routing Information Protocol) 路由信息协议 RPC (Remote Procedure Call) 远程过程调用 RR (Resource Record) 资源记录 RST (ReSeT) TCP首部中的复位标志 RTO (Retransmission Time Out) 重传超时 RTT (Round-Trip Time) 往返时间 SACK (Selective ACKnowledgment) 有选择的确认 SLIP (Serial Line Internet Protocol) 串行线路I n t e r n e t协议 SMI (Structure of Management Information) 管理信息结构 SMTP (Simple Mail Transfer Protocol) 简单邮件传送协议 SNMP (Simple Network Management Protocol) 简单网络管理协议 SSAP (Source Service Access Point) 源服务访问点 SSRR (Strict Source and Record Route) 严格的源站及记录路由 SWS (Silly Window Syndrome) 糊涂窗口综合症 SYN (SYNchronous) TCP首部中的同步序号标志 TCP (Transmission Control Protocol) 传输控制协议 TFTP (Trivial File Transfer Protocol) 简单文件传送协议 TLI (Transport Layer Interface) 运输层接口 TTL (Ti m e - To-Live) 生存时间或寿命 TUBA (TCP and UDP with Bigger Addresses) 具有更长地址的T C P和U D P Telnet 远程终端协议 UA (User Agent) 用户代理 UDP (User Datagram Protocol) 用户数据报协议 URG (URGent) TCP首部中的紧急指针标志 UTC (Coordinated Universal Time) 协调的统一时间 UUCP (Unix-to-Unix CoPy) Unix到U n i x的复制 WAN (Wide Area Network) 广域网 WWW (World Wide Web) 万维网 XDR (eXternal Data Representation) 外部数据表示 XID (transaction ID) 事务标识符 XTI (X/Open Transport Layer Interface) X/ O p e n运输层接口

    标签: tcp 协议

    上传时间: 2013-11-13

    上传用户:tdyoung

  • 4位数一段设定6位数累积计数器

    特点 最高輸入頻率 10KHz 显示范围0-9999(一段设定)0至999999累积量 计数速度 50/10000脈波/秒可选择 输入脈波具有预设刻度功能 累积量同步(批量)或非同步(批次)计数可选择 数位化指拨设定操作简易 计数暂时停止功能 1组报警功能 2:主要規格 脈波輸入型式: Jump-pin selectable current sourcing(NPN) or current sinking (PNP) 脉波触发电位: HI bias (CMOS) (VIH=7.5V, VIL=5.5V) LO bias (TTL) (VIH=3.7V, VIL=2.0V) 最高输入频率: <10KHz (up,down,up/down mode) 输出动作时间 : 0.1 to 99.9 second adjustable 输出复归方式: Manual(N) or automatic (R or C) can be modif 继电器容量: AC 250V-5A, DC 30V-7A 显示值范围: 0-9999(PV,SV) 0-999999(TV) 显示幕: Red high efficiency LEDs high 7.0mm (.276")(PV,SV) Red high efficiency LEDs high 9.2mm (.36")(TV) 参数设定方式: Touch switches 感应器电源: 12VDC +/-3%(<60mA) 记忆方式: Non-volatile E2PROM memory 绝缘耐压能力: 2KVac/1 min. (input/output/power) 1600Vdc (input/output) 使用环境条件: 0-50℃(20 to 90% RH non-condensed) 存放环境条件: 0-70℃(20 to 90% RH non-condensed) CE认证: EN 55022:1998/A1:2000 Class A EN 61000-3-2:2000 EN 61000-3-3:1995/A1:2001 EN 55024:1998/A1:2001

    标签: 设定 累积计数器

    上传时间: 2013-10-24

    上传用户:wvbxj