富士通单片机MB902420系列 extINT Project: All external Interrupt-Pins INT0 .. INT7 will be enabled. A falling edge on INTx will toggle PDR4_P4x in order to toggle the LEDx of the Flash-CAN-100P Board e.g. falling edge on INT3 will result in LED D3 will toggleP47..P40 (UserLEDs of FlashCan100P) and will send out again as byte-packages to ID#2 Receive-Buffer #1 : basic can Transmit-Buffer #6 : full-can ID #2
标签： Interrupt-Pins external Project enabled
上传时间： 2016-04-27
上传用户：waizhang
vhdl编写，8b—10b 编解码器设计 Encoder: 8b/10b Encoder (file: 8b10b_enc.vhd) Synchronous clocked inputs (latched on each clock rising edge) 8-bit parallel unencoded data input KI input selects data or control encoding Asynchronous active high reset initializes all logic Encoded data output 10-bit parallel encoded output valid 1 clock later Decoder: 8b/10b Decoder (file: 8b10b_dec.vhd) Synchronous clocked inputs (latched on each clock rising edge) 10-bit parallel encoded data input Asynchronous active high reset initializes all logic Decoded data, disparity and KO outputs 8-bit parallel unencoded output valid 1 clock later
上传时间： 2016-05-05
上传用户：gundamwzc
sfrmat is a Matlab function that provides a spatial frequency response* (SFR) from a digital image file containing a slanted-edge feature. The specific edge-gradient algorithm follows the intent of the standard ISO 12233, developed by Technical Committee ISI/TC 42, for resolution measurements for electronic still pictorial cameras.
标签： frequency function provides response
上传时间： 2014-01-20
上传用户：qunquan
Top module name : SHIFTER (File name : SHIFTER.v) 2. Input pins: SHIFT [3:0], IN [15:0], SIGN, RIGHT. 3. Output pins: OUT [15:0]. 4. Input signals generated from test pattern are latched in one cycle and are synchronized at clock rising edge. 5. The SHIFT signal describes the shift number. The shift range is 0 to 15. 6. When the signal RIGHT is high, it shifts input data to right. On the other hand, it shifts input data to left. 7. When the signal SIGN is high, the input data is a signed number and it shifts with sign extension. However, the input data is an unsigned number if the signal SIGN is low. 8. You can only use following gates in Table I and need to include the delay information (Tplh, Tphl) in your design.
上传时间： 2013-12-12
上传用户：himbly
Top module name : SHIFTER (File name : SHIFTER.v) 2. Input pins: SHIFT [3:0], IN [15:0], SIGN, RIGHT. 3. Output pins: OUT [15:0]. 4. Input signals generated from test pattern are latched in one cycle and are synchronized at clock rising edge. 5. The SHIFT signal describes the shift number. The shift range is 0 to 15. 6. When the signal RIGHT is high, it shifts input data to right. On the other hand, it shifts input data to left. 7. When the signal SIGN is high, the input data is a signed number and it shifts with sign extension. However, the input data is an unsigned number if the signal SIGN is low. 8. You can only use following gates in Table I and need to include the delay information (Tplh, Tphl) in your design.
上传时间： 2014-01-19
上传用户：三人用菜
ST32 基于（英蓓特）STM32V100的EXTI程序 This example shows how to configure an external interrupt line. In this example, the EXTI line 9 is configured to generate an interrupt on each falling edge. In the interrupt routine a led connected to PC.06 is toggled. This led will be toggled due to the softawre interrupt generated on EXTI Line9 then at each falling edge.
标签： configure interrupt external example
上传时间： 2016-11-17
上传用户：GavinNeko
selects the mux channel and configures the MAX197 for second write pulse, written with ACQMOD = 0, termi- either unipolar or bipolar input range. A write pulse (WR nates acquisition and starts conversion on WR°Os risin + CS) can either start an acquisition interval or initiate a edge (Figure 6). However, if the second control byte combined acquisition plus conversion. The sampling contains ACQMOD = 1, an indefinite acquisition interval interval occurs at the end of the acquisition interval. is restarted. The ACQMOD bit in the input control byte offer
标签： configures the selects channel
上传时间： 2013-12-08
上传用户：kjl
selects the mux channel and configures the MAX197 for second write pulse, written with ACQMOD = 0, termi- either unipolar or bipolar input range. A write pulse (WR nates acquisition and starts conversion on WR°Os risin + CS) can either start an acquisition interval or initiate a edge (Figure 6). However, if the second control byte combined acquisition plus conversion. The sampling contains ACQMOD = 1, an indefinite acquisition interval interval occurs at the end of the acquisition interval. is restarted. The ACQMOD bit in the input control byte offer
标签： configures the selects channel
上传时间： 2016-12-24
上传用户：朗朗乾坤
selects the mux channel and configures the MAX197 for second write pulse, written with ACQMOD = 0, termi- either unipolar or bipolar input range. A write pulse (WR nates acquisition and starts conversion on WR°Os risin is restarted. The ACQMOD bit in the input control byte offer+ CS) can either start an acquisition interval or initiate a edge (Figure 6). However, if the second control byte combined acquisition plus conversion. The sampling contains ACQMOD = 1, an indefinite acquisition interval interval occurs at the end of the acquisition interval.
标签： configures the selects channel
上传时间： 2016-12-24
上传用户：yzhl1988
97 law to enhance the classic procedure Ridge wavelet extraction Modulus maximum for the wavelet edge detection Small spectral analysis method mallat classic procedure
标签： wavelet extraction the procedure
上传时间： 2014-01-08
上传用户：xg262122
