fir ISP design fir VHDL VHDL编程滤波的硬件描述语言实现,包括VHDL语言和verilog语言
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汇集 component+design 相关的电路原理图、PCB工程文件、单片机/FPGA源代码、数据手册与应用设计方案。
Component to show a lcd screen. in full color and max. performens
DDC design based on AD6634,useful
PCA人脸识别 This package implements basic Principal Component Analysis in Matlab and tests is with grayscale portion of the FERET data…
High-Speed and Embedded Systems Design
XPMenu is a Delphi component to mimic Office XP menu and toolbar style. Copyright (C) 2001 Khaled Shagrouni.
于毕业设计与论文以及做课题用-MSK Simulink simulation program for the design and graduation thesis topic, and makin
于毕业设计与论文以及做课题用-MSK Simulink simulation program for the design and graduation thesis topic, and making use -Design and graduation t…
Data Structures And Algorithms With Object-Oriented Design Patterns In Python (2003) source code and
Data Structures And Algorithms With Object-Oriented Design Patterns In Python (2003) source code and html file
Complete support for EBNF notation; Object-oriented parser design; C++ output; Deterministic bottom-
Complete support for EBNF notation; Object-oriented parser design; C++ output; Deterministic bottom-up "shift-reduce" parsing; SLR…
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