clocking
共 15 篇文章
clocking 相关的电子技术资料，包括技术文档、应用笔记、电路设计、代码示例等，共 15 篇文章，持续更新中。
Digital System clocking
·Digital System clocking
MC68LC302低功耗集成多协议微处理器参考手册
Section 2– Configuration, Clocking, Low Power Modes, and<BR>Internal Memory Map<BR>1. SCCE2 Register
Memory Interfaces Data Capture Using Direct Clocking Technique
<P>This application note describes the direct-clocking data capture technique for memory<BR>interfac
FPGA Spartan6 CSG324数据手册
<p>The BUFIO2 clocking region column lists the BUFIO2 clock sources that connect to the I/Oclock input for the associated pin. For more information see Clock Inputs and BUFIO2Clocking Regions in Chapt
vivado集成开发环境时序约束介绍
<p>本文主要介绍如何在Wado设计套件中进行时序约束，原文出自 xilinx中文社区。</p><p>1 Timing Constraints in Vivado-UCF to xdcVivado软件相比于sE的一大转变就是约束文件，5E软件支持的是UcF（User Constraints file，而 Vivado软件转换到了XDc（Xilinx Design Constraints）。XDC主
Vivado时序约束
Synopsys' widely-used design constraints format, known as SDC, describes the "design intent" and surrounding constraints for synthesis, clocking, timing, power, test and environmental and operating co
tas3204
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VIP专区-单片机源代码精选合集系列（69）
<b>eeworm.com VIP专区 单片机源码系列 68</b><br/><font color="red">资源包含以下内容：</font><br/>1. AN010101基于LM3S2000系列CAN控制器的驱动库.pdf<br/>2. 定压输入6000VDC隔离非稳压单路输出.pdf<br/>3. LM3S系列单片机扩展按键及数码管及RTC应用笔记.pdf<br/>4. Stellari
XAPP1065 - 利用Spartan-6 FPGA设计扩频时钟发生器
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Consumer display applications commonly use high-speed LVDS interfaces to transfer videodata. Spread-spectrum clocking can be used to address electromagnetic compatibility (EMC)i
逐次逼近式AD转换器研究
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<span style="color: rgb(26, 24, 24); font-family: Arial, Helvetica, sans-serif; line-height: 15px; ">A tutorial on SAR type A/D converters, this note contains detailed information on several 12-b
数字集成电路设计Digital Integrated Circuit Design
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This unique guide to designing digital VLSI circuits takes a top-down approach, reflecting the natureof the design process in industry. Starting with architecture design, the bo
带有SerDes接口的PLB千兆位级以太网MAC
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This application note describes a reference system which illustrates how to build an embeddedPowerPC® system using the Xilinx 1-Gigabit Ethernet Media Access Controller processor core.This
XAPP1065 - 利用Spartan-6 FPGA设计扩频时钟发生器
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Consumer display applications commonly use high-speed LVDS interfaces to transfer videodata. Spread-spectrum clocking can be used to address electromagnetic compatibility (EMC)i
Clocking Options for Stellaris
<P>The main oscillator allows either a crystal or single-ended input clock signal. Cost-sensitive<BR>applications typically use an external crystal with the on-chip oscillator circuit since it is the
用单片机配置FPGA—PLD设计技巧
<P>用单片机配置FPGA—PLD设计技巧</P>
<P>Configuration/Program Method for Altera Device</P>
<P>Configure the FLEX Device</P>
<P>You can use any Micro-Controller to configure the FLEX device<BR>–the main idea is c