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单片机开发 There are many different (and often confusing) terms associated with clock-based devices. This appl
There are many different (and often confusing) terms associated
with clock-based devices. This application note attempts
to clarify these terms, and hence serves as a comprehensive
reference on clock terminology. This application note can be
divided into two sections. The first section describes and ...
VHDL/FPGA/Verilog Clock based on the VHDL design language, the revised time alarm can be set up
Clock based on the VHDL design language, the revised time alarm can be set up
单片机编程 基于AVR单片机Mega16的电子时钟设计
Mega16是一款采用先进RISC精简指令，内置A/D的8位单片机，可支持低电压联机 Flash和EEPROM 写入功能；同时还支持 Basic和C 等高级语言编程。用它设计电子时钟不仅成本低，硬件简单，而且很容易实现系统移植。介绍了如何利用AVR系列单片机Mega16及1602字符液晶来设计电子时钟的方法，同时给出了相应的电路原理及部分语言程序 ...
微处理器开发 pic16f8 based clock, it display the time on the TV display. This include source code and sch
pic16f8 based clock, it display the time on the TV display. This include source code and sch
通讯/手机编程 Jitter is extremely important in systems using PLL-based clock drivers. The effects of jitter range
Jitter is extremely important in systems using PLL-based
clock drivers. The effects of jitter range from not having any
effect on system operation to rendering the system completely
non-functional. This application note provides the reader
with a clear understanding of jitter in high-speed systems. ...
通讯/手机编程 Cypress Semiconductor makes a variety of PLL-based clock generators. This application note provides
Cypress Semiconductor makes a variety of PLL-based clock
generators. This application note provides a set of recommendations
to optimize usage of Cypress clock devices in a
system. The application note begins with recommended termination
techniques for clock generators. Subsequently, power
supply fi ...
模拟电子 02 calgary PhD A Java-Based Wireless Framework for Location-Based Services Applications.pdf
资料->【E】光盘论文->【E1】斯坦福博士论文->02 calgary PhD A Java-Based Wireless Framework for Location-Based Services Applications.pdf
教程资料 FPGA-based high-order FIR filter design
FPGA-based high-order FIR filter design
教程资料 Digital Down Converter Design based on FPGA
Digital Down Converter Design based on FPGA.
教程资料 fpga based jpge 压缩算法
fpga based jpge 压缩算法，性能不错，