clock+jitter 技术资料

基于fpga的多功能数字钟，时分秒显示，整点报时，可设置时间段不报时，开发平台quartus ii，语言是verilog

用msp430单片机实现时钟，考虑到低功耗编程。

My thesis entitled \"fpga digital clock,\" immature, to enlighten

Analog clock component.

Clock division document

Clock basic msp430f149

Clock-calendar circuit.

Digital CLock Upload!

multi-function clock

Realtime clock DS12c887