MAXQUSBJTAGOW评估板软件:关键特性 Easily Load and Debug Code Interface Provides In-Application Debugging Features Step-by-Step Execution Tracing Breakpointing by Code Address, Data Memory Address, or Register Access Data Memory View and Edit Supports Logic Levels from 1.1V to 3.6V Supports JTAG and 1-Wire Protocols Each Adapter Has Its Own Unique Serial ID, Allowing Multiple Adapters to be Connected Without COM Port Conflicts Has In-Field Upgradable capability if Firmware Needs to be Upgraded Enclosure Protects from Shorts and ESD
标签： MAXQUSBJTAGOW 评估板 软件
上传时间： 2013-10-24
上传用户：teddysha
MAXQUSBJTAGOW评估板软件:关键特性 Easily Load and Debug Code Interface Provides In-Application Debugging Features Step-by-Step Execution Tracing Breakpointing by Code Address, Data Memory Address, or Register Access Data Memory View and Edit Supports Logic Levels from 1.1V to 3.6V Supports JTAG and 1-Wire Protocols Each Adapter Has Its Own Unique Serial ID, Allowing Multiple Adapters to be Connected Without COM Port Conflicts Has In-Field Upgradable capability if Firmware Needs to be Upgraded Enclosure Protects from Shorts and ESD
标签： MAXQUSBJTAGOW 评估板 软件
上传时间： 2013-11-23
上传用户：truth12
中文版详情浏览：http://www.elecfans.com/emb/fpga/20130715324029.html Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications. The UltraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the UltraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation. Some of the UltraScale architecture breakthroughs include: • Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50% • Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability • Potential timing-closure problems and interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization • 3D IC integration makes it possible to build larger devices one process generation ahead of the current industr y standard • Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bandwidth is available within even smaller system power budgets • Greatly enhanced DSP and packet handling The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.
标签： UltraScale Xilinx 架构
上传时间： 2013-11-21
上传用户：wxqman
VS1002D ADPCM RECORDING INSTRUCTIONS v 1.0 (C) 2004-09-23 VLSI SOLUTION OY This is a software package to patch VS1002d ADPCM recording capability. It is explained in VS10XX Application Notes, available at http://www.vlsi.fi/download/ See also source code src/microcontrol.c for example.
标签： INSTRUCTIONS RECORDING SOLUTION softwar
上传时间： 2014-01-05
上传用户：894898248
Hard-decision decoding scheme Codeword length (n) : 31 symbols. Message length (k) : 19 symbols. Error correction capability (t) : 6 symbols One symbol represents 5 bit. Uses GF(2^5) with primitive polynomial p(x) = X^5 X^2 + 1 Generator polynomial, g(x) = a^15 a^21*X + a^6*X^2 + a^15*X^3 + a^25*X^4 + a^17*X^5 + a^18*X^6 + a^30*X^7 + a^20*X^8 + a^23*X^9 + a^27*X^10 + a^24*X^11 + X^12. Note: a = alpha, primitive element in GF(2^5) and a^i is root of g(x) for i = 19, 20, ..., 30. Uses Verilog description with synthesizable RTL modelling. Consists of 5 main blocks: SC (Syndrome Computation), KES (Key Equation Solver), CSEE (Chien Search and Error Evaluator), Controller and FIFO Register.
标签： symbols length Hard-decision Codeword
上传时间： 2014-07-08
上传用户：曹云鹏
The aim of this application note is to show to scan the 4x4 matrix keypad multiplexed with a four 7-segment display. The software attached to this application note scans the pressed key and displays it on the multiplexed 7- segment LEDs. This application note makes obvious Interrupt capability of the STR710 device to offer a better key scan .
标签： application multiplexed matrix keypad
上传时间： 2015-09-13
上传用户：thuyenvinh
开源中间件 导入Hibernate相关的包进该项目： 选中项目名称后单击鼠标右键，从弹出的右键快捷菜单中选择“MyEclise-> Add Hibernate capability”
上传时间： 2014-08-17
上传用户：cjf0304
Author: wei liu Summary: simulation of binary and non-binary bch decoder MATLAB Release: R14SP1 Required Products: Communications Toolbox Description: simulation of binary bch decoding algorithm for bch(n, k) with t bits error correction capability.
标签： simulation non-binary Summary Release
上传时间： 2014-01-10
上传用户：frank1234
16 relay output channels and 16 isolated digital input channels LED indicators to show activated relays Jumper selectable Form A/Form B-type relay output channel Output status read-back Keep relay output values when hot system reset High-voltage isolation on input channels(2,500 VDC) Hi ESD protection(2,00VDC) High over-voltage protection(70VDC) Wide input range(10~50VDC) Interrupt handling capability High-density DB-62 connector Board ID
标签： channels indicators activated isolated
上传时间： 2016-02-15
上传用户：dongbaobao
Integration的EZMac Plus，对于开发IA4420/4421很有用！ Variable packet length protocol with packet forwarding capability MAC layer for simplifying EZRadio designs
标签： Integration EZMac Plus
上传时间： 2016-05-12
上传用户：alan-ee
