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DSP编程 This example streams input from a ADC source to a DAC. An analog signal is acquired block-by-block

This example streams input from a ADC source to a DAC. An analog signal is acquired block-by-block into SDRAM from the ADC (an AD9244 in this example). The frames are then output with a one-frame delay to the DAC (an AD9744 in this example). In this example, no processing is done on the frames. The ...
https://www.eeworm.com/dl/516/240027.html
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通讯/手机编程 The IEEE Multipath Channel block simulates an indoor UWB channel as described in "A Channel Model fo

The IEEE Multipath Channel block simulates an indoor UWB channel as described in "A Channel Model for Ultrawideband Indoor Communications" by J.R. Foerster, M. Pendergrass and A.F. Molisch, November 2003, and attempts to incorporate the processes used in their MATLAB scripts.
https://www.eeworm.com/dl/527/150236.html
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matlab例程 This program simulates plant identification using frequency block least mean square (FBLMS) alogrith

This program simulates plant identification using frequency block least mean square (FBLMS) alogrithm reference: 《LMS算法的频域快速实现》 LMS is modified by XXX in XXX place, see details in XXX relevant document
https://www.eeworm.com/dl/665/265510.html
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软件设计/软件工程 SDRAM 参考设计:主要包括The following figure shows a high-level block diagram for this reference design follo

SDRAM 参考设计:主要包括The following figure shows a high-level block diagram for this reference design followed by a brief description of each sub-section. The design consists of: · PowerPC processor · PLB-OPB bridge · BlockRAM Memory Controller · SDRAM Controller · Two GPIO ports · A UART Por ...
https://www.eeworm.com/dl/684/266335.html
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教程资料 altera fpga 基于vhdl,实现vga的同步block

altera fpga 基于vhdl,实现vga的同步block.
https://www.eeworm.com/dl/fpga/doc/18337.html
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PCB相关 Protel 自定义Title Block方法

Protel 自定义Title Block方法
https://www.eeworm.com/dl/501/21959.html
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教程资料 UG341-LogiCORE Endpoint Block

UG341 - LogiCORE™ Endpoint Block Plus v1.6 for PCI Express® 用户指南
https://www.eeworm.com/dl/fpga/doc/32725.html
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可编程逻辑 7.4 基于IP CORE的BLOCK RAM设计修改稿

7.4 基于IP CORE的BLOCK RAM设计修改稿。
https://www.eeworm.com/dl/kbcluoji/38710.html
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可编程逻辑 Protel 自定义Title Block方法

Protel 自定义Title Block方法
https://www.eeworm.com/dl/kbcluoji/39619.html
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可编程逻辑 UG341-LogiCORE Endpoint Block

UG341 - LogiCORE™ Endpoint Block Plus v1.6 for PCI Express® 用户指南
https://www.eeworm.com/dl/kbcluoji/40413.html
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