//=== === === === === === === === === === === === === === = //函数说明 //函数名称：PolyFit //函数功能：最小二乘法曲线拟合 //使用方法：double *x ---- 存放n个数据点的X坐标 // double *y ---- 存放n个数据点的Y坐标 // int n -------- 给定数据点个数 // double *a ---- 返回m-1次拟合多项式的m个系数 // int m -------- 拟合多项式的项数，即拟合多项式的最高次为m-1。要求m<=n,且 // m<=20。若m>n或m>20，则本函数自动按m=min{n,20}处理 // double *dt --- dt[0]返回拟合多项式与各数据点误差的平方和；dt[1]返回拟合多 // 项式与各数据点的误差绝对值之和；dt[2]返回拟合多项式与各数据 // 点误差绝对值的最大值 //注意事项：拟合多项式的形式为 y = b0 + b1*(x-Xavr)...
上传时间： 2015-07-19
上传用户：waizhang
The module includes three sub_module:FDivider128,generates the 1/128 frequency, MD_Counter8Zero, generates the flute when the posedge, MD_Counter8One,generates the flute when the negedge.The aim of the module is to generate the mended miller code to be the source of the MillerDecode. 输入的数据以下降沿采样，有效输入范围为上升沿前一点，输入数据包括1 b0+有效数据+1 b0 Operating Rule: R_DATAUNCODE must be synchronous with R_ACTIVE
标签： MD_Counter sub_module 128 generates
上传时间： 2013-12-30
上传用户：Miyuki
FPGA片内FIFO读写测试Verilog逻辑源码Quartus工程文件+文档说明，使用 FPGA 内部的 FIFO 以及程序对该 FIFO 的数据读写操作。FPGA型号Cyclone4E系列中的EP4CE6F17C8，Quartus版本17.1。timescale 1ns / 1ps//////////////////////////////////////////////////////////////////////////////////module fifo_test( input clk, //50MHz时钟 input rst_n //复位信号，低电平有效 );//-----------------------------------------------------------localparam W_IDLE = 1;localparam W_FIFO = 2; localparam R_IDLE = 1;localparam R_FIFO = 2; reg[2:0] write_state;reg[2:0] next_write_state;reg[2:0] read_state;reg[2:0] next_read_state;reg[15:0] w_data; //FIFO写数据wire wr_en; //FIFO写使能wire rd_en; //FIFO读使能wire[15:0] r_data; //FIFO读数据wire full; //FIFO满信号 wire empty; //FIFO空信号 wire[8:0] rd_data_count; wire[8:0] wr_data_count; ///产生FIFO写入的数据always@(posedge clk or negedge rst_n)begin if(rst_n == 1'b0) write_state <= W_IDLE; else write_state <= next_write_state;endalways@(*)begin case(write_state) W_IDLE: if(empty == 1'b1) //FIFO空， 开始写FIFO next_write_state <= W_FIFO; else next_write_state <= W_IDLE; W_FIFO: if(full == 1'b1) //FIFO满 next_write_state <= W_IDLE; else next_write_state <= W_FIFO; default: next_write_state <= W_IDLE; endcaseendassign wr_en = (next_write_state == W_FIFO) ? 1'b1 : 1'b0; always@(posedge clk or negedge rst_n)begin if(rst_n == 1'b0) w_data <= 16'd0; else if (wr_en == 1'b1) w_data <= w_data + 1'b1; else w_data <= 16'd0; end///产生FIFO读的数据always@(posedge clk or negedge rst_n)begin if(rst_n == 1'b0) read_state <= R_IDLE; else read_state <= next_read_state;endalways@(*)begin case(read_state) R_IDLE: if(full == 1'b1) //FIFO满, 开始读FIFO next_read_state <= R_FIFO; else next_read_state <= R_IDLE; R_FIFO: if(empty == 1'b1)
上传时间： 2021-12-19
上传用户：20125101110
