Microchip 单片机的速度和复杂性已经到达足以要 求降低电源电压的程度，并正在向 5V 电源电压以 下转换。但问题是绝大多数接口电路仍然是为 5V 电源而设计的。这就意味着，作为设计人员，我们 现在面临着连接 3.3V 和 5V 系统的任务。此外， 这个任务不仅包括逻辑电平转换，同时还包括为 3.3V 系统供电、转换模拟信号使之跨越 3.3V/5V 的 障碍。 技巧和诀窍 DS41285A_CN 第 2 页 . 2006 Microchip Technology Inc. 本 《技巧和诀窍》提供了一些电源供电组件、数 字电平转换组件甚至模拟转换组件，以解决所面临 的挑战。全书对每种转换均给出了多种选择方案， 从单片 （All-in-One）接口器件到低成本的分立解 决方案都有涉及。简而言之，无论导致转换的原因 是复杂性、成本还是尺寸，设计人员处理 3.3V 挑 战可能需要的全部组件均在本文有所讨论。
上传时间： 2013-10-30
上传用户：wqxstar
Designing read/write device (RWD) units for industrial RF-Identification applications is strongly facilitated by the NXP Semiconductors HITAG Reader Chip HTRC110. All needed function blocks, like the antenna driver, modulator demodulator and antenna diagnosis unit, are integrated in the HTRC110. Therefore only a minimum number of additional passive components are required for a complete RWD. This Application Note describes how to design an industrial RF-Identification system with the HTRC110. The major focus is dimensioning of the antenna, all other external components including clock and power supply, as well as the demodulation principle and its implementatio
上传时间： 2013-10-22
上传用户：zhengjian
在航电系统维护过程中，为解决定位故障的效率和降低维修成本等问题，提出了基于ICD（Interface Control Document，接口控制文件）的1553B总线的信息监控系统模型。该系统运用数据采集卡对总线中传输的信号有无失真、偏差等电气特性进行检测，并使用1553B通讯卡通过测控软件LabWindows/CVI编程与ICD数据库的动态链接，实现总线信息的解析和故障的判断。与传统的维护过程相比，这种模型能够从信号的电气特性以及信息的解析等全方位的去检测判断故障的来源，并且能够广泛在其他1553B总线系统内扩展应用。验证表明该监控系统可以对总线信息进行快速有效地监测分析，能满足应用需求。 Abstract: In the process of avionics system maintenance， to solve the problems such as improving the efficiency of fast orientation to troubles and reducing maintenance cost， system of 1553B bus information monitor model based on ICD was proposed. The system observed whether the data which transmitted on the bus appear distortion and deviation by using data acquisition card. And using 1553B communication card programming of the measure software LabWindows/CVI and the dynamic linking of ICD database， message analysis and fault estimation could be realized. Compared with traditional maintenance， this model can all-dimensionally detect and analyze the source of faults from both electrical characteristics of the signal and message analysis， and it can be widely applied in the other 1553B system. Experiment shown that this monitor system can effectively detect and analyze the bus message and can meet the application requirements.
上传时间： 2013-11-23
上传用户：18752787361
高可靠性8位/16位All flash MCU结构、特点及应用 目录NEC的MCU产品系列介绍NEC “全闪存单片机” 的特点NEC 8位MCU产品NEC 8位MCU特色功能介绍NEC 16位MCU特色功能介绍
上传时间： 2013-11-22
上传用户：ouyangmark
附件有51单片机加上sl811读写U盘的源程序和原理图 /*--------------------------------------------------------------------------AT89X52.H Header file for the low voltage Flash Atmel AT89C52 and AT89LV52.Copyright (c) 1995-1996 Keil Software, Inc. All rights reserved.--------------------------------------------------------------------------*/ #ifndef AT89X52_HEADER_FILE#define AT89X52_HEADER_FILE 1 /*------------------------------------------------Byte Registers------------------------------------------------*/sfr P0 = 0x80;sfr SP = 0x81;sfr DPL = 0x82;sfr DPH = 0x83;sfr PCON = 0x87;sfr TCON = 0x88;sfr TMOD = 0x89;sfr TL0 = 0x8A;sfr TL1 = 0x8B;sfr TH0 = 0x8C;sfr TH1 = 0x8D;sfr P1 = 0x90;sfr SCON = 0x98;sfr SBUF = 0x99;sfr P2 = 0xA0;sfr IE = 0xA8;sfr P3 = 0xB0;sfr IP = 0xB8;sfr T2CON = 0xC8;sfr T2MOD = 0xC9;sfr RCAP2L = 0xCA;sfr RCAP2H = 0xCB;sfr TL2 = 0xCC;sfr TH2 = 0xCD;sfr PSW = 0xD0;sfr ACC = 0xE0;sfr B = 0xF0;
上传时间： 2014-01-05
上传用户：lnnn30
This overview guide describes all the peripherals available for TMS320x28xx and TMS320x28xxx devices.Section 2 shows the peripherals used by each device. Section 3 provides descriptions of the peripherals.You can download the peripheral guide by clicking on the literature number, which is linked to the portable document format (pdf) file.
上传时间： 2013-11-21
上传用户：HGH77P99
Xilinx UltraScale™ 架构针对要求最严苛的应用，提供了前所未有的ASIC级的系统级集成和容量。 UltraScale架构是业界首次在All Programmable架构中应用最先进的ASIC架构优化。该架构能从20nm平面FET结构扩展至16nm鳍式FET晶体管技术甚至更高的技术，同 时还能从单芯片扩展到3D IC。借助Xilinx Vivado®设计套件的分析型协同优化，UltraScale架构可以提供海量数据的路由功能，同时还能智能地解决先进工艺节点上的头号系统性能瓶颈。 这种协同设计可以在不降低性能的前提下达到实现超过90%的利用率。 UltraScale架构的突破包括： • 几乎可以在晶片的任何位置战略性地布置类似于ASIC的系统时钟，从而将时钟歪斜降低达50% • 系统架构中有大量并行总线，无需再使用会造成时延的流水线，从而可提高系统速度和容量 • 甚至在要求资源利用率达到90%及以上的系统中，也能消除潜在的时序收敛问题和互连瓶颈 • 可凭借3D IC集成能力构建更大型器件，并在工艺技术方面领先当前行业标准整整一代 • 能在更低的系统功耗预算范围内显著提高系统性能，包括多Gb串行收发器、I/O以及存储器带宽 • 显著增强DSP与包处理性能 赛灵思UltraScale架构为超大容量解决方案设计人员开启了一个全新的领域。
标签： UltraScale Xilinx 架构
上传时间： 2013-11-17
上传用户：皇族传媒
中文版详情浏览：http://www.elecfans.com/emb/fpga/20130715324029.html Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications. The UltraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the UltraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation. Some of the UltraScale architecture breakthroughs include: • Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50% • Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability • Potential timing-closure problems and interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization • 3D IC integration makes it possible to build larger devices one process generation ahead of the current industr y standard • Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bandwidth is available within even smaller system power budgets • Greatly enhanced DSP and packet handling The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.
标签： UltraScale Xilinx 架构
上传时间： 2013-11-13
上传用户：瓦力瓦力hong
There is no doubt that remote controls are extremely popular and it has become very hard to imagine a world without them. They are used to control all manner of house appliances like the TV set, the stereo, the VCR, and the satellite receiver.
上传时间： 2013-11-13
上传用户：顶得柱
稀疏表示分类算法（Sparse Representation-based Classification，SRC）在人脸数据库上有很高的识别性能。然而，对于姿态变化，SRC的识别效果并不理想。针对SRC算法不能解决测试样本与训练样本存在偏移误差的问题，本文提出了基于SRC的改进算法。该算法将每一类的训练样本单独作为训练字典，利用迭代校正和基于金字塔分层机构的运动偏移估计方法得到最终的偏移量，最后对校正后的测试样本使用SRC算法实现分类。实验结果表明该方法对于有偏移误差的人脸图像具有较好的鲁棒性及识别率。
上传时间： 2013-11-15
上传用户：haiya2000
