Board(印刷电路板)的缩写。
上传时间： 2015-01-01
上传用户：ppeyou
Allegro15[1].X培训教材
上传时间： 2014-01-08
上传用户：qzhcao
Spartan-3E Starter Kit Board User Guide英语版的介绍，很适合初学者学习学习
标签： Spartan Starter Board Guide
上传时间： 2013-11-19
上传用户：ruan2570406
The Virtex-4 features, such as the programmable IDELAY and built-in FIFO support, simplifythe bridging of a high-speed, PCI-X core to large amounts of DDR-SDRAM memory. Onechallenge is meeting the PCI-X target initial latency specification. PCI-X Protocol Addendum tothe PCI Local Bus Specification Revision 2.0a ([Ref 6]) dictates that when a target signals adata transfer, "the target must do so within 16 clocks of the assertion of FRAME#." PCItermination transactions, such as Split Response/Complete, are commonly used to meet thelatency specifications. This method adds complexity to the design, as well as additional systemlatency. Another solution is to increase the ratio of the memory frequency to the PCI-X busfrequency. However, this solution increases the required power and clock resource usage.
上传时间： 2013-11-24
上传用户：18707733937
This application note covers the design considerations of a system using the performance features of the LogiCORE™ IP Advanced eXtensible Interface (AXI) Interconnect core. The design focuses on high system throughput through the AXI Interconnect core with F MAX and area optimizations in certain portions of the design. The design uses five AXI video direct memory access (VDMA) engines to simultaneously move 10 streams (five transmit video streams and five receive video streams), each in 1920 x 1080p format, 60 Hz refresh rate, and up to 32 data bits per pixel. Each VDMA is driven from a video test pattern generator (TPG) with a video timing controller (VTC) block to set up the necessary video timing signals. Data read by each AXI VDMA is sent to a common on-screen display (OSD) core capable of multiplexing or overlaying multiple video streams to a single output video stream. The output of the OSD core drives the DVI video display interface on the board. Performance monitor blocks are added to capture performance data. All 10 video streams moved by the AXI VDMA blocks are buffered through a shared DDR3 SDRAM memory and are controlled by a MicroBlaze™ processor. The reference system is targeted for the Virtex-6 XC6VLX240TFF1156-1 FPGA on the Xilinx® ML605 Rev D evaluation board
上传时间： 2013-11-23
上传用户：shen_dafa
支持X/YModem和cis_b+协议的串口通讯程序
上传时间： 2014-01-17
上传用户：qweqweqwe
支持X/Y/Z Modem协议的传输文件的通讯程序
上传时间： 2015-01-03
上传用户：xg262122
X Windows下的迷宫程序
上传时间： 2015-01-04
上传用户：372825274
支持Windows 3.x、Windows 9x平台上的中文（GB、Big5）、日文（Shift JIS、EUC JIS)、韩文（KS C 5601）、HZ码的显示与输入,智能内码识别，支持屏幕取词翻译的16位程序(VC1.5编译)。作者：朱佳良
上传时间： 2013-12-28
上传用户：003030
支持SSL v2/v3, TLS, PKCS #5, PKCS #7, PKCS #11, PKCS #12, S/MIME, X.509v3证书等安全协议或标准的开发库编译用到NSPR
上传时间： 2014-01-27
上传用户：sammi
