The LogiCORE™ GTP Wizard automates the task of creating HDL wrappers to configure the high-speed serial GTP transceivers in Virtex™-5 LXT and SXT devices. The menu-driven interface allows one or more GTP transceivers to be configured using pre-definedtemplates for popular industry standards, or from scratch, to support a wide variety of custom protocols.The Wizard produces a wrapper, an example design, and a testbench for rapid integration and verification of the serial interface with your custom function Features• Creates customized HDL wrappers to configureVirtex-5 RocketIO™ GTP transceivers• Users can configure Virtex-5 GTP transceivers toconform to industry standard protocols usingpredefined templates, or tailor the templates forcustom protocols• Included protocol templates provide support for thefollowing specifications: Aurora, CPRI, FibreChannel 1x, Gigabit Ethernet, HD-SDI, OBSAI,OC3, OC12, OC48, PCI Express® (PCIe®), SATA,SATA II, and XAUI• Automatically configures analog settings• Each custom wrapper includes example design, testbench; and both implementation and simulation scripts
标签: Transceiver Virtex Wizar GTP
上传时间: 2013-10-20
上传用户:dave520l
UG203-Virtex-5 PCB设计指南
上传时间: 2013-10-16
上传用户:helmos
UG190 Virtex-5 用户指南
上传时间: 2015-01-01
上传用户:xiaohanhaowei
The data plane of the reference design consists of a configurable multi-channel XBERT modulethat generates and checks high-speed serial data transmitted and received by the MGTs. Eachchannel in the XBERT module consists of two MGTs (MGTA and MGTB), which physicallyoccupy one MGT tile in the Virtex-4 FPGA. Each MGT has its own pattern checker, but bothMGTs in a channel share the same pattern generator. Each channel can load a differentpattern. The MGT serial rate depends on the reference clock frequency and the internal PMAdivider settings. The reference design can be scaled anywhere from one channel (two MGTs)to twelve channels (twenty-four MGTs).
上传时间: 2013-12-25
上传用户:jkhjkh1982
xilinx Virtex architecture
标签: architecture xilinx Virtex
上传时间: 2015-02-06
上传用户:6546544
xilinx Virtex floorprint
标签: floorprint xilinx Virtex
上传时间: 2014-11-29
上传用户:cmc_68289287
VHDL编写的PCI代码,PCI2.2兼容,Xillinx Virtex与Spantan II 优化,33M主频,32位宽度,全目标功能等.
标签: PCI Spantan Xillinx Virtex
上传时间: 2015-06-03
上传用户:大融融rr
SRL16是Virtex器件中的一个移位寄存器查找表。它有4个输入用来选择输出序列的长度。使用XCV50-6器件实现,共占用5个Slice。用来生成gold码。
上传时间: 2015-06-16
上传用户:水中浮云
Xilinx的培训教程的源码 Virtex
上传时间: 2015-08-31
上传用户:JIUSHICHEN
XAPP858 - 利用 Virtex-5 FPGA 实现的高性能 DDR2 SDRAM 接口数据采集 本应用指南描述了用于实现 667 Mbps(333 MHz)高性能 DDR2 SDRAM 接口的控制器和数据采集的技巧。 本数据采集技巧使用了输入串行器/解串器(ISERDES)和输出串行器/解串器(OSERDES)的功能。
上传时间: 2014-01-19
上传用户:sk5201314