The MAX9257/MAX9258 programmable serializer/deserializer (SerDes) devices transfer both Video data and control signals over the same twisted-pair cable. However, control data can only be transmitted during the vertical blank time, which is indicated by the control-channel-enabled output (CCEN) signal. The electronic control unit (ECU) firmware designer needs to know how quickly to respond to the CCEN signal before it times out and how to calculate this duration. This application note describes how to calculate the duration of the CCEN for the MAX9257/MAX9258 SerDes chipset. The calculation is based on STO timeout, clock frequency, and UART bit timing. The CCEN duration is programmable and can be closed if not in use.
上传时间： 2014-01-24
上传用户：xingisme
为解决传统可视倒车雷达视频字符叠加器结构复杂，可靠性差，成本高昂等问题，在可视倒车雷达设计中采用视频字符发生器芯片MAX7456。该芯片集成了所有用于产生用户定义OSD，并将其插入视频信号中所需的全部功能，仅需少量的外围阻容元件即可正常工作。给出了以MAX7456为核心的可视倒车雷达的软、硬件实现方案及设计实例。该方案具有电路结构简单、价格低廉、符合人体视觉习惯的特点。经实际装车测试，按该方案设计的可视倒车雷达视场清晰、提示字符醒目、工作可靠，可有效降低驾驶员倒车时的工作强度、减少倒车事故的发生。 Abstract: A new Video and text generation chip，MAX7456，was used in the design of Video parking sensor in order to simplify system structure，improve reliability and reduce cost. This chip included all the necessary functions to generate user-defined OSDs and to add them into the Video signals. It could be put into work with addition of just a small number of resistances and capacitors. This paper provided software and hardware implementation solutions and design example based on the chip. The system had the characteristics of simplicity in circuit structure，lower cost，and comfort for the nature of human vision. Loading road test demonstrates high Video and text display quality and reliable performance，which makes the driver easy to see backward and reduces chance of accidents.
上传时间： 2013-12-10
上传用户：qiaoyue
基于ADSP-BF561的数字摄像系统设计Design of Digital Video Camera System Based on Digital Signal ProcessorADSP-BF561（浙江大学 信息与通信工程研究所，浙江 杭州 310027） 马海杰, 刘云海摘要：介绍了基于ADI双核的数字信号处理芯片ADSP-BF561 的数字摄像系统实现方案。系统包括硬件和软件两部分，硬件主要有ADSP-BF561及其外围电路、音视频模数/数模转换、CF卡/微硬盘接口等部分。软件主要有操作系统及音视频编解码算法等部分。关键词：ADSP-BF561 ;数字摄像机;微硬盘;MPEG-4;A/D;D/A中图分类号:TN948.41文献标识码:AAbstract: An implementation of digital Video camera system based on ADI dual core digital signal processor ADSP-BF561 is introduced. The system can be divided into two parts——hardware and software design. The hardware design includes ADSP-BF561 and perpheral apparatus, A/D,D/A, CF card or Microdrive and so on. The software includes operating system , audio and Video coding algorithm.Key words: ADSP-BF561; digital Video camera; microdrive; MPEG-4;A/D;D/A
上传时间： 2013-11-10
上传用户：yl1140vista
为了扩大监控范围，提高资源利用率，降低系统成本，提出了一种多通道视频切换的解决方案。首先从视频信号分离出行场信号，然后根据行场信号由DSP和FPGA产生控制信号，控制多路视频通道之间的切换，从而实现让一个视频处理器同时监控不同场景。实验结果表明，该方案可以在视频监控告警系统中稳定、可靠地实现视频通道的切换。 Abstract: To expand the scope of monitoring， improve resource utilization， reduce system cost， a multiple Video channels signal switching method is pointed out in this paper. First， horizontal sync signal and field sync signal from the Video signal are separated， then control signal according to the sync signal by DSP and FPGA is generated to control the switching between multiple Video channels. Thus， it achieves to make a Video processor to monitor different place. Experimental results show that the method can realize Video channel switching reliably， and is applied in the Video monitoring warning system successfully.
上传时间： 2013-11-09
上传用户：不懂夜的黑
The SDI standards are the predominant standards for uncompressed digital Videointerfaces in the broadcast studio and Video production center. The first SDI standard,SD-SDI, allowed standard-definition digital Video to be transported over the coaxial cableinfrastructure initially installed in studios to carry analog Video. Next, HD-SDI wasto support high-definition Video. Finally, dual link HD-SDI and 3G-SDIdoubled the bandwidth of HD-SDI to support 1080p (50 Hz and 60 Hz) and other Videoformats requiring more bandwidth than HD-SDI provides.
上传时间： 2013-10-08
上传用户：yjj631
This application note covers the design considerations of a system using the performance features of the LogiCORE™ IP Advanced eXtensible Interface (AXI) Interconnect core. The design focuses on high system throughput through the AXI Interconnect core with F MAX and area optimizations in certain portions of the design. The design uses five AXI Video direct memory access (VDMA) engines to simultaneously move 10 streams (five transmit Video streams and five receive Video streams), each in 1920 x 1080p format, 60 Hz refresh rate, and up to 32 data bits per pixel. Each VDMA is driven from a Video test pattern generator (TPG) with a Video timing controller (VTC) block to set up the necessary Video timing signals. Data read by each AXI VDMA is sent to a common on-screen display (OSD) core capable of multiplexing or overlaying multiple Video streams to a single output Video stream. The output of the OSD core drives the DVI Video display interface on the board. Performance monitor blocks are added to capture performance data. All 10 Video streams moved by the AXI VDMA blocks are buffered through a shared DDR3 SDRAM memory and are controlled by a MicroBlaze™ processor. The reference system is targeted for the Virtex-6 XC6VLX240TFF1156-1 FPGA on the Xilinx® ML605 Rev D evaluation board
上传时间： 2013-11-14
上传用户：fdmpy
VGA 是视频图形阵列（Video Graphics Array）的简称，是IBM 于1987 年提出的一个使用模拟信号的图形显示标准。最初的VGA 标准最大只能支持640*480 分辨率的显示器，而为了适应大屏幕的应用，视频电气标准化组织VESA（Video Electronics StandardsAssociation 的简称）将VGA 标准扩展为SVGA 标准，SVGA 标准能够支持更大的分辨率。人们通常所说的VGA 实际上指的就是VESA 制定的SVGA 标准。(1). VGA 接口VGA 采用15 针的接口，用于显示的接口信号主要有5 个：1 个行同步信号、1 个场同步信号以及3 个颜色信号，接口还包含自测试以及地址码信号，一般由不同的制造商定义，主要用来进行测试及支持其它功能。
上传时间： 2013-10-27
上传用户：541657925
MPEG（Moving Picture Experts Group）和VCEG（Video Coding Experts Group）已经联合开发了一个比早期研发的MPEG 和H.263 性能更好的视频压缩编码标准，这就是被命名为AVC（Advanced Video Coding），也被称为ITU-T H.264 建议和MPEG-4 的第10 部分的标准，简称为H.264/AVC 或H.264。这个国际标准已经与2003 年3 月正式被ITU-T 所通过并在国际上正式颁布。为适应高清视频压缩的需求，2004 年又增加了FRExt 部分；为适应不同码率及质量的需求，2006 年又增加了可伸缩编码 SVC。
上传时间： 2013-11-19
上传用户：dancnc
Agilent AN 154 S-Parameter Design Application Note S参数的设计与应用 The need for new high-frequency, solid-state circuitdesign techniques has been recognized both by microwaveengineers and circuit designers. These engineersare being asked to design solid state circuitsthat will operate at higher and higher frequencies.The development of microwave transistors andAgilent Technologies’ network analysis instrumentationsystems that permit complete network characterizationin the microwave frequency rangehave greatly assisted these engineers in their work.The Agilent Microwave Division’s lab staff hasdeveloped a high frequency circuit design seminarto assist their counterparts in R&D labs throughoutthe world. This seminar has been presentedin a number of locations in the United States andEurope.From the experience gained in presenting this originalseminar, we have developed a four-part Videotape, S-Parameter Design Seminar. While the technologyof high frequency circuit design is everchanging, the concepts upon which this technologyhas been built are relatively invariant.The content of the S-Parameter Design Seminar isas follows:
标签： S参数
上传时间： 2013-12-19
上传用户：aa54
提出了一种以ARM微处理器为控制核心的远程无线视频监控终端的设计方案，其监控终端的硬件设计包括视频采集处理、中央管理控制、无线传输3个模块。并给出了监控终端的软件开发平台和开发模式的系统启动代码、嵌入式Linux系统移植以及驱动程序和应用程序。测试结果表明，该监控终端设计方案合理、有效，基本满足监控需求。 Abstract: A remote wireless Video monitoring terminal design， which uses ARM microprocessor as its core control， is proposed in this paper.The hardware design of monitoring terminal system is composed of the Video acquisition and processing module， the central management and control module， wireless transmission module.Meanwhile the monitoring terminal-s software development platform and development patterns are designed. Also the design of the system-s start codes， embedded Linux system-s transplantation process， driver and the corresponding applications are given. The results showed that the monitoring terminal design is reasonable， effective， basically meet monitoring requirements.
上传时间： 2013-11-13
上传用户：wanqunsheng
