·详细说明：一些嵌入式系统编程的电子书，包括嵌入式的C编程，TI的RTOS以及LINUX文件列表: DSPBIOS 5.30 Textual Configuration.pdf DSPBIOS Driver.pdf DSPBIOS Timing Benchmarks for.pdf dspRTOS.pdf&nbs
上传时间： 2013-05-17
上传用户：wangchong
A complete design for a data acquisition card for the IBM PC is detailed in this application note. Additionally, C language code is provided to allow sampling of data at speed of more than 20kHz. The speed limitation is strictly based on the execution speed of the "C" data acquisition loop. A "Turbo" XT can acquire data at speeds greater than 20kHz. Machines with 80286 and 80386 processors can go faster than 20kHz. The computer that was used as a test bed in this application was an XT running at 4.77MHz and therefore all system Timing and acquisition time measurements are based on a 4.77MHz clock speed.
上传时间： 2013-10-29
上传用户：BOBOniu
高速数字系统设计下载pdf:High-Speed Digital SystemDesign—A Handbook ofInterconnect Theory and DesignPracticesStephen H. HallGarrett W. HallJames A. McCallA Wiley-Interscience Publication JOHN WILEY & SONS, INC.New York • Chichester • Weinheim • Brisbane • Singapore • TorontoCopyright © 2000 by John Wiley & Sons, Inc.speeddigital systems at the platform level. The book walks the reader through everyrequired concept, from basic transmission line theory to digital Timing analysis, high-speedmeasurement techniques, as well as many other topics. In doing so, a unique balancebetween theory and practical applications is achieved that will allow the reader not only tounderstand the nature of the problem, but also provide practical guidance to the solution.The level of theoretical understanding is such that the reader will be equipped to see beyondthe immediate practical application and solve problems not contained within these pages.Much of the information in this book has not been needed in past digital designs but isabsolutely necessary today. Most of the information covered here is not covered in standardcollege curricula, at least not in its focus on digital design, which is arguably one of the mostsignificant industries in electrical engineering.The focus of this book is on the design of robust high-volume, high-speed digital productssuch as computer systems, with particular attention paid to computer busses. However, thetheory presented is applicable to any high-speed digital system. All of the techniquescovered in this book have been applied in industry to actual digital products that have beensuccessfully produced and sold in high volume.Practicing engineers and graduate and undergraduate students who have completed basicelectromagnetic or microwave design classes are equipped to fully comprehend the theorypresented in this book. At a practical level, however, basic circuit theory is all thebackground required to apply the formulas in this book.
上传时间： 2013-10-26
上传用户：缥缈
随着系统设计复杂性和集成度的大规模提高，电子系统设计师们正在从事100MHZ以上的电路设计，总线的工作频率也已经达到或者超过50MHZ，有一大部分甚至超过100MHZ。目前约80% 的设计的时钟频率超过50MHz，将近50% 以上的设计主频超过120MHz，有20%甚至超过500M。当系统工作在50MHz时，将产生传输线效应和信号的完整性问题；而当系统时钟达到120MHz时，除非使用高速电路设计知识，否则基于传统方法设计的PCB将无法工作。因此，高速电路信号质量仿真已经成为电子系统设计师必须采取的设计手段。只有通过高速电路仿真和先进的物理设计软件，才能实现设计过程的可控性。传输线效应基于上述定义的传输线模型，归纳起来，传输线会对整个电路设计带来以下效应。 · 反射信号Reflected signals · 延时和时序错误Delay & Timing errors · 过冲(上冲/下冲)Overshoot/Undershoot · 串扰Induced Noise (or crosstalk) · 电磁辐射EMI radiation
上传时间： 2013-11-15
上传用户：lx9076
This document provides practical, common guidelines for incorporating PCI Express interconnect layouts onto Printed Circuit Boards (PCB) ranging from 4-layer desktop baseboard designs to 10- layer or more server baseboard designs. Guidelines and constraints in this document are intended for use on both baseboard and add-in card PCB designs. This includes interconnects between PCI Express devices located on the same baseboard (chip-to-chip routing) and interconnects between a PCI Express device located “down” on the baseboard and a device located “up” on an add-in card attached through a connector. This document is intended to cover all major components of the physical interconnect including design guidelines for the PCB traces, vias and AC coupling capacitors, as well as add-in card edge-finger and connector considerations. The intent of the guidelines and examples is to help ensure that good high-speed signal design practices are used and that the Timing/jitter and loss/attenuation budgets can also be met from end-to-end across the PCI Express interconnect. However, while general physical guidelines and suggestions are given, they may not necessarily guarantee adequate performance of the interconnect for all layouts and implementations. Therefore, designers should consider modeling and simulation of the interconnect in order to ensure compliance to all applicable specifications. The document is composed of two main sections. The first section provides an overview of general topology and interconnect guidelines. The second section concentrates on physical layout constraints where bulleted items at the beginning of a topic highlight important constraints, while the narrative that follows offers additional insight.
上传时间： 2013-10-15
上传用户：busterman
While simplicity and high effi ciency (for cool running) areno longer optional features in isolated power supplies, itis traditionally diffi cult to achieve both. Achieving higheffi ciency often requires the use of advanced topologiesand home-brewed secondary synchronous rectifi cationschemes once reserved only for higher power applications.This only adds to the parts count and to the designcomplexity associated with the reference and optocouplercircuits typically used to maintain isolation. Fortunately, abreakthrough IC makes it possible to achieve both high efficiency and simplicity in a synchronous fl yback topology.The LT®3825 simplifi es and improves the performance oflow voltage, high current fl yback supplies by providingprecise synchronous rectifi er Timing and eliminating theneed for optocoupler feedback while maintaining excellentregulation and superior loop response.
上传时间： 2013-10-16
上传用户：wayne595
Abstract: As electronic systems take over many of the mechanical functions in a car—ranging from engine Timing to steering andbraking—there is a growing concern about fault tolerance. There should not be a single point of failure that would prevent a car fromat least "limping" off the road or making it to the nearest service station. Redundant systems, watchdog timers, and other controlcircuits are used to reroute signals and perform other functions that ensure that a vehicle can safely make it off the road when afailure occurs.
上传时间： 2013-11-10
上传用户：diets
Demonstration circuit 1562A is an engineering toolto design and evaluate the LTC699X-X family ofTimerBlox circuits. The center section of the boardcontains a pre-configured TimerBlox function.DC1562A comes in twelve Timing function variationsas outlined in Table 1.Surrounding the center board is a ”playground”prototyping area. The prototyping area has padsfor Dip-8, S8, MS8, or S6 packages with breadboarding connections to each pin and two convenientpower buses and ground bus surrounding theentire area. This area is for conditioning signals tocontrol the timer function and for adding loads controlled in time.
上传时间： 2013-10-18
上传用户：如果你也听说
The MAX9257/MAX9258 programmable serializer/deserializer (SerDes) devices transfer both video data and control signals over the same twisted-pair cable. However, control data can only be transmitted during the vertical blank time, which is indicated by the control-channel-enabled output (CCEN) signal. The electronic control unit (ECU) firmware designer needs to know how quickly to respond to the CCEN signal before it times out and how to calculate this duration. This application note describes how to calculate the duration of the CCEN for the MAX9257/MAX9258 SerDes chipset. The calculation is based on STO timeout, clock frequency, and UART bit Timing. The CCEN duration is programmable and can be closed if not in use.
上传时间： 2014-01-24
上传用户：xingisme
设计一种基于AT89C52的语音录放系统，利用单片机、ISD2560语音录放器件、麦克风、扬声器等元器件实现硬件电路的设计，并利用C51高级语言设计ISD2560器件控制字的写入和定时中断程序。经软硬件调试，结果表明该系统录放效果良好，具有一定的工程实用价值。 Abstract: Voice recording and playback system based on AT89C52is designed in this paper.Using the single-chip microcomputer，voice recording and playback chip ISD2560，microphone and speaker to realize the hardware circuit design.Writing ISD2560control words and Timing interrupt procedures are designed by C51advanced language.Through the hardware and software test,voice recording and playback system play better voice,and this system has some engineering practical values.
上传时间： 2013-10-20
上传用户：ywcftc277
