Joey is j2me client server application for for mobile platform. Build on TOP j2mepolish
标签： application j2mepolish for platform
上传时间： 2016-09-29
上传用户：sz_hjbf
3D Statistical shape analysis by SHPARM method: code and paper. From the TOP group at UNC.
标签： Statistical analysis SHPARM method
上传时间： 2016-10-20
上传用户：wfl_yy
iic总线控制器VHDL实现 -- VHDL Source Files: i2c.vhd -- TOP level file i2c_control.vhd -- control function for the I2C master/slave shift.vhd -- shift register uc_interface.vhd -- uC interface function for an 8-bit 68000-like uC upcnt4.vhd -- 4-bit up counter i2c_timesim.vhd -- post-route I2C simulation netlist
标签： VHDL c_control vhd control
上传时间： 2016-10-30
上传用户：woshiayin
TOP module name : SHIFTER (File name : SHIFTER.v) 2. Input pins: SHIFT [3:0], IN [15:0], SIGN, RIGHT. 3. Output pins: OUT [15:0]. 4. Input signals generated from test pattern are latched in one cycle and are synchronized at clock rising edge. 5. The SHIFT signal describes the shift number. The shift range is 0 to 15. 6. When the signal RIGHT is high, it shifts input data to right. On the other hand, it shifts input data to left. 7. When the signal SIGN is high, the input data is a signed number and it shifts with sign extension. However, the input data is an unsigned number if the signal SIGN is low. 8. You can only use following gates in Table I and need to include the delay information (Tplh, Tphl) in your design.
上传时间： 2013-12-13
上传用户：himbly
TOP module name : SHIFTER (File name : SHIFTER.v) 2. Input pins: SHIFT [3:0], IN [15:0], SIGN, RIGHT. 3. Output pins: OUT [15:0]. 4. Input signals generated from test pattern are latched in one cycle and are synchronized at clock rising edge. 5. The SHIFT signal describes the shift number. The shift range is 0 to 15. 6. When the signal RIGHT is high, it shifts input data to right. On the other hand, it shifts input data to left. 7. When the signal SIGN is high, the input data is a signed number and it shifts with sign extension. However, the input data is an unsigned number if the signal SIGN is low. 8. You can only use following gates in Table I and need to include the delay information (Tplh, Tphl) in your design.
上传时间： 2014-01-20
上传用户：三人用菜
The DSKs or eZdspTM LF2407 and the DMC1500 make up a table TOP motor development system which allows engineers and software developers to evaluate certain characteristics of the TMS320F240, TMS320F243, and TMS320LF2407 DSPs to determine if the processor meets the designers application requirements. Evaluators can create software to execute onboard or expand the system in a variety of ways.
标签： development eZdspTM system allow
上传时间： 2013-12-24
上传用户：zhuoying119
英文 网络课件 Computer Networking: A TOP Down Approach Featuring the Internet, 3rd edition. Jim Kurose, Keith Ross Addison-Wesley, July 2004.
标签： Networking Featuring Computer Approach
上传时间： 2014-07-24
上传用户：123啊
A TOP-Down Verilog-A Design on the digital phase-lockedmloop
标签： phase-lockedmloop Verilog-A TOP-Down digital
上传时间： 2013-12-02
上传用户：silenthink
FPGA程序的TOP.v文件，主要实现DDS信号发生器功能，通过定时器，可简单实现输出幅值无极跳变
上传时间： 2013-11-26
上传用户：曹云鹏
本程序包含：EEPROM的功能模型(eeprom.v)、读/写EEPROM的verilog HDL 行为模块（eeprom_wr.v）、信号产生模块（signal.v）和顶层模块(TOP.v) ，这样可以有一个完整的EEPROM的控制模块和测试文件，本文件通过测试。
标签： EEPROM eeprom_wr verilog eeprom
上传时间： 2017-01-22
上传用户：lanjisu111
