This a script for working with short TCP files with several source nodes, sharing a single bottleneck link. It is used to show how with proper choice of CIR, marking decreases losses of vulnerable packets (syns etc).
标签： with bottlenec working several
上传时间： 2015-05-11
上传用户：aa17807091
Single Output 神经网络实例演示1
上传时间： 2014-06-09
上传用户：xiaoyunyun
Document type: Recommended Practice Document subtype: Document stage: Draft Recommended Practice Document language: English
标签： Document Recommended Practice subtype
上传时间： 2013-12-24
上传用户：saharawalker
cp2102 is a Single-Chip USB to UART Data Transfer
标签： Single-Chip Transfer 2102 Data
上传时间： 2014-01-21
上传用户：l254587896
for serial communication single-slave with buffer sum check
标签： communication single-slave buffer serial
上传时间： 2015-06-06
上传用户：hxy200501
Single-layer neural networks can be trained using various learning algorithms. The best-known algorithms are the Adaline, Perceptron and Backpropagation algorithms for supervised learning. The first two are specific to single-layer neural networks while the third can be generalized to multi-layer perceptrons.
标签： Single-layer algorithms best-known networks
上传时间： 2015-06-17
上传用户：赵云兴
The same two-stage decoder as above. However, when transforming the symbols prior to Viterbi decoding, the amplitude information is ignored and only the phase of the received symbol is employed in the metric computation stage.
标签： transforming two-stage However decoder
上传时间： 2015-07-05
上传用户：sevenbestfei
以SPCE061A单片机（ Single Chip Micyoco）为核心，通过DDS合成技术设计制作了一个步进值能任意调节的多功能信号源。该信号源在1KHz～10MHz范围能输出稳定可调的正弦波，并具有AM、FM、ASK和PSK等调制功能。信号输出部分采用低损耗电流反馈型宽带运放作电压放大，很好地解决了带宽和带负载能力的要求。系统带中文显示和键盘控制功能，操作简便，实现效果良好。 内含 原程序，正弦信号发生器的pCB原理图，以及一些相关论文。
上传时间： 2015-07-07
上传用户：lizhizheng88
关于FPGA流水线设计的论文 This work investigates the use of very deep pipelines for implementing circuits in FPGAs, where each pipeline stage is limited to a single FPGA logic element (LE). The architecture and VHDL design of a parameterized integer array multiplier is presented and also an IEEE 754 compliant 32-bit floating-point multiplier. We show how to write VHDL cells that implement such approach, and how the array multiplier architecture was adapted. Synthesis and simulation were performed for Altera Apex20KE devices, although the VHDL code should be portable to other devices. For this family, a 16 bit integer multiplier achieves a frequency of 266MHz, while the floating point unit reaches 235MHz, performing 235 MFLOPS in an FPGA. Additional cells are inserted to synchronize data, what imposes significant area penalties. This and other considerations to apply the technique in real designs are also addressed.
标签： investigates implementing pipelines circuits
上传时间： 2015-07-26
上传用户：CHINA526
OMAP1510/1610/2420系列处理器2-stage bootloader（X-Loader）文档说明！适用于NAND Flash启动。
标签： bootloader X-Loader Flash stage
上传时间： 2014-01-22
上传用户：chenjjer
