串口通迅测试，当收到8个以上字符时就将收到的字符再发送出去，波特率为9600。基于LPCEB2000-S的串口程序
上传时间： 2013-11-04
上传用户：dvfeng
中文版详情浏览：http://www.elecfans.com/emb/fpga/20130715324029.html Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications. The UltraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the UltraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation. Some of the UltraScale architecture breakthroughs include: • Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50% • Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability • Potential timing-closure problems and interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization • 3D IC integration makes it possible to build larger devices one process generation ahead of the current industr y standard • Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bandwidth is available within even smaller system power budgets • Greatly enhanced DSP and packet handling The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.
标签： UltraScale Xilinx 架构
上传时间： 2013-11-21
上传用户：wxqman
This application note describes how to implement the Bus LVDS (BLVDS) interface in the supported Altera ® device families for high-performance multipoint applications. This application note also shows the performance analysis of a multipoint application with the Cyclone III BLVDS example.
标签： Implementing LVDS 522 Bus
上传时间： 2013-10-26
上传用户：苏苏苏苏
本文档说明实际建立一个CAN-bus网络时，对网络布线和CAN 接口的设计，对通讯电 缆和连接器的选择，以及一些保障通讯可靠、提高抗干扰能力的经验措施。
上传时间： 2013-11-09
上传用户：AISINI005
CAN（Controller Area Network——控制器局域网）是一种由 CAN 控制器组成的高性能串行数据局域通信网络，是国际上应用最广泛的现场总线之一。它最早由德国 Bosch 公司于 1984 年推出，最初用于汽车内部测量与执行部件之间的数据通信。CAN-bus 总线模型符合 OSI 的 7 层结构；CAN-bus 规范已被 ISO 估计标准组织制定为国际标准。
上传时间： 2013-11-13
上传用户：lvzhr
CANWiFi-600/622是为电信级应用而设计的工业级CAN转WiFi接口卡/设配器，它内部集成了一路/两路CAN-bus 接口、一个以太网接口、一路无线WIFI接口以及TCP/IP 协议栈，符合 IEEE802.11b/g/n 标准，具有传输速率高、接收灵敏度高和传输距离远等特点，CANWIFI-600/622通过与 WiFi 基站设备（或无线宽带路由器或无线AP）一起配合使用，设备可以在与其它拥有相同网络ID的接入点间自由的漫游，通过无线WiFi把CAN网络接入Wireless Ethernet。用户利于它可以轻松完成CAN-bus 网络和Wireless Ethernet的互连互通，进一步拓展CAN-bus 网络的范围。
上传时间： 2015-01-02
上传用户：cooran
The high defi nition multimedia interface (HDMI) is fastbecoming the de facto standard for passing digitalaudio and video data in home entertainment systems.This standard includes an I2C type bus called a displaydata channel (DDC) that is used to pass extended digitalinterface data (EDID) from the sinkdevice (such as adigital TV) to the source device (such as a digital A/Vreceiver). EDID includes vital information on the digitaldata formats that the sink device can accept. The HDMIspecifi cation requires that devices have less than 50pFof input capacitance on their DDC bus lines, which canbe very diffi cult to meet. The LTC®4300A’s capacitancebuffering feature allows devices to pass the HDMI DDCinput capacitance compliance test with ease.
上传时间： 2013-11-21
上传用户：tian126vip
16kb/s Low Delay CELP 算法
上传时间： 2015-01-03
上传用户：huangld
支持SSL v2/v3, TLS, PKCS #5, PKCS #7, PKCS #11, PKCS #12, S/MIME, X.509v3证书等安全协议或标准的开发库编译用到NSPR
上传时间： 2014-01-27
上传用户：sammi
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上传时间： 2013-12-20
上传用户：sdq_123
