Registers
共 85 篇文章
Registers 相关的电子技术资料，包括技术文档、应用笔记、电路设计、代码示例等，共 85 篇文章，持续更新中。
The VGA example generates a 320x240 diffusion-limited-aggregation (DLA) on Altera DE2 board. A DLA i
The VGA example generates a 320x240 diffusion-limited-aggregation (DLA) on Altera DE2 board. A DLA is a clump formed by sticky particles adhering to an existing structure. In this design, we start wit
Builder uses to integrate a larger system module. Each component consists of a structured set of fi
Builder uses to integrate a larger system module. Each component
consists of a structured set of files within a directory.
The files in a component directory serve the following
The RS232 UART Core
51单片机读写u盘(含源程序和原理图)
<P>附件有51单片机加上sl811读写U盘的源程序和原理图</P>
<P>/*--------------------------------------------------------------------------<BR>AT89X52.H</P>
<P>Header file for the low voltage Flash Atmel AT89C52 and AT89LV52.
MSP430f2013 ADC, LCD drivers using 74168 shift registers
MSP430f2013 ADC, LCD drivers using 74168 shift registers
MSP-FET430P140 Demo - USART0, SPI Interface to HC165/164 Shift Registers Description: Demonstrate
MSP-FET430P140 Demo - USART0, SPI Interface to HC165/164 Shift Registers
Description: Demonstrate USART0 in two-way SPI mode. Data are read from
an HC165, and same data written back to the HC164.
vhdl程序源代码
vhdl程序源代码，包括Combinational Logic
Counters
Shift Registers
Memory
State Machines
Registers
Systems
ADC and DAC
Arithmetic等
this a pack include source code for quartus 2. It is an implementation of the LC2. The LC-2 compu
this a pack include source code for quartus 2.
It is an implementation of the LC2. The LC-2 computer is described in Introduction to Computing Systems from Bits & Gates to C & Beyond by Yale Patt a
ARMask.The ARM has six operating modes: • User (unprivileged mode under which most tasks run)
ARMask.The ARM has six operating modes:
• User (unprivileged mode under which most tasks run)
• FIQ (entered when a high priority (fast) interrupt is raised)
• IRQ (entered when a lo
VHDL实现SPI功能源代码 -- The SPI bus is a 3 wire bus that in effect links a serial shift -- register betw
VHDL实现SPI功能源代码
-- The SPI bus is a 3 wire bus that in effect links a serial shift
-- register between the "master" and the "slave". Typically both the
-- master and slave have an 8 bit shift regist
SL811开发资料_包含源程序_电路图_芯片资料
SL811开发资料_包含源程序_电路图_芯片资料:SL811HS Embedded USB Host/Slave Controller.The SL811HS is an Embedded USB Host/Slave Controller capable of communicate with either full-speed or low-speed USB peripherals. The
RW - Read & Write utility, for hardware engineers, firmware (BIOS) engineers, driver developers, QA
RW - Read & Write utility, for hardware engineers, firmware (BIOS) engineers, driver developers, QA engineers, performance test engineers, diagnostic engineers, etc., This utility access almost all th
PCI-Express Lane Test Utility. Validates negotiated lane capability registers, returns error codes,
PCI-Express Lane Test Utility. Validates negotiated lane capability registers, returns error codes, supports multiple vendor/device ID s
CAT93C46 器件数据手册
The CAT93C46 is a 1 kb Serial EEPROM memory device which is<BR>configured as either 64 registers of 16 bits (ORG pin at VCC) or 128<BR>registers of 8 bits (ORG pin at GND). Each register can be writte
PCA9555 16bit I2C-bus and SMBu
<P>The PCA9555 is a 24-pin CMOS device that provides 16 bits of General Purpose parallel<BR>Input/Output (GPIO) expansion for I2C-bus/SMBus applications and was developed to<BR>enhance the NXP Semicon
LPC1700以太网MIIM接口应用笔记
The LPC1700 Ethernet block contains a full featured 10 Mbps or 100 Mbps Ethernet MAC (Media Access Controller) designed to provide optimized performance through the use of DMA hardware acceleration. F
带有SerDes接口的PLB千兆位级以太网MAC
<div>
This application note describes a reference system which illustrates how to build an embeddedPowerPC® system using the Xilinx 1-Gigabit Ethernet Media Access Controller processor core.This
HITECH与电脑的通信协议
1 Communication Protocol (Computer as master)<br />
<br />
The communication protocol describes here allows your computer to 
XAPP1042-利用GPIO实现以太网PHY寄存器访问
<div>
The XPS Ethernetlite peripheral does not provide any mechanism to access the Ethernet PHYregisters. These registers are used to configure auto negotiation parameters and to obtain PHYstatus. Th
Using the Stellaris Microcontr
<P>Luminary Micro Stellaris™ microcontrollers that are equipped with an analog-to-digital converter(ADC), use an innovative sequence-based sampling architecture designed to be extremely flexible
基于FPGA的可编程m序列发生器的实现
· 摘要： 本文研究了由线性反馈移位寄存器(Linear Feedback Shift Registers,LFSR)生成m序列的原理,并对LFSR电路结构作了改进,利用基于现代DSP技术的DSP Builder软件,设计了一种周期、相位可调的m序列发生器.经调试与仿真,结果表明该方法硬件结构简单、开发周期短,为系统设计或测试带来很大的便利.