This project provides a general Purpose library which implements read and write support for MMC, SD and SDHC memory cards. Written in ANSI C portable for several Microcontrollers.
标签： implements provides project general
上传时间： 2014-01-21
上传用户：zhangyigenius
MicroC/OS-II The Real-Time Kernel Second Edition By Jean J. Labrosse CMP Books, CMP Media LLC Copyright 2002 by CMP Books ISBN 1-57820-103-9 CMP Books CMP Media LLC 1601 West 23rd Street, Suite 200 Lawrence, Kansas 66046 785-841-1631 www.cmpbooks.com email: books@cmp.com The programs and applications on this disk have been carefully tested, but are not guaranteed for any particular Purpose. The publisher does not offer any warranties and does not guarantee the accuracy, adequacy, or completeness of any information and is not responsible for any errors or omissions or the results obtained from use of such information.
标签： MicroCOS_II 嵌入式 实时操作系统
上传时间： 2013-06-09
上传用户：zhyiroy
可重构计算技术兼具通用处理器(General-Purpose Processor，GPP)和专用集成电路(Application Specific Integr—ated Circuits，ASIC)的特点，既可以提供硬件高速的特性，又具有软件可以重新配置的特性。而动态部分可重构技术是可重构计算技术的最新进展之一。该技术的要点就是在系统正常工作的情况下，修改部分模块的功能，而系统其它模块能够照常运行，这样既节约硬件资源，又增强了系统灵活性。 可重构SoC既可以在处理器上进行编程又可以改变FPGA内部的硬件结构，这使得SoC系统既具有处理器善于控制和运算的特点，又具FPGA灵活的重构特点；由于处理器和FPGA硬件是在同一块硅片上，使得它们之间的通信宽带大大提高，这种平台很适合于容错算法的实现。 本文基于863计划项目；动态重构计算机的可信实现关键技术，重点研究应用于恶劣环境中FPGA自我容错的体系结构，提出了一套完整的SoC系统的容错设计方案，并研究其实现技术，设计实现了实现该技术的硬件平台和软件算法，并验证成功。 论文取得了如下的创新性研究成果： 1、设计了实现动态重构技术的硬件平台，包括高性能的FPGA(内含入式处理器PowcrPC)、PROM、SRAM、FLASH、串口通信等硬件模块。 2、说明了动态重构技术的设计规范和设计流程，实现动态重构技术。 3、提出了一种基于动态重构实现容错的方法，不需要外部处理器干预，由嵌入式处理器负责管理整个过程。 4、设计并实现了嵌入式处理器运行时需要的软件，主要有两个功能，首先是从CF卡中读入重构所需的配置文件，并将配置文件写进FPGA内部的配置存储器中，改变FPGA内部的功能。其次，是实现容错技术的算法。
上传时间： 2013-04-24
上传用户：edrtbme
■ High Performance, Low Power AVR® 8-Bit Microcontroller ■ Advanced RISC Architecture –120 Powerful Instructions – Most Single Clock Cycle Execution –32 x 8 General Purpose Working Registers –Fully Static Operation
标签： Atmel
上传时间： 2013-06-01
上传用户：tccc
The Purpose of this note is to present how to use the ST7 PWM/BRM for the generation of a50Hz si
上传时间： 2013-05-31
上传用户：huyanju
The Purpose of this application note is to show an example of how a digital potentiometer can be used in thefeedback loop of a step-up DC-DC converter to provide calibration and/or adjustment of the output voltage.The example circuit uses a MAX5025 step-up DC-DC converter (capable of generating up to 36V,120mWmax) in conjunction with a DS1845, 256 position, NV digital potentiometer. For this example, the desiredoutput voltage is 32V, which is generated from an input supply of 5V. The output voltage can be adjusted in35mV increments (near 32V) and span a range wide enough to account for resistance, potentiometer and DCDCconverter tolerances (27.6V to 36.7V).
上传时间： 2014-12-23
上传用户：781354052
Digital-to-analog converters (DACs) are prevalent inindustrial control and automated test applications.General-Purpose automated test equipment often requiresmany channels of precisely controlled voltagesthat span several voltage ranges. The LTC2704 is ahighly integrated 16-bit, 4-channel DAC for high-endapplications. It has a wide range of features designed toincrease performance and simplify design.
上传时间： 2013-11-22
上传用户：元宵汉堡包
Linear Technology’s High Frequency Product lineupincludes a variety of RF I/Q modulators. The Purpose ofthis application note is to illustrate the circuits requiredto interface these modulators with several popular D/Aconverters. Such circuits typically are required to maximizethe voltage transfer from the DAC to the baseband inputsof the modulator, as well as provide some reconstructionfi ltering.
上传时间： 2013-10-18
上传用户：FreeSky
PCI ExpressTM Architecture Add-in Card Compliance Checklist for the PCI Express Base 1.0a SpecificationThe PCI Special Interest Group disclaims all warranties and liability for the use of this document and the information contained herein and assumes no responsibility for any errors that may appear in this document, nor does the PCI Special Interest Group make a commitment to update the information contained herein.Contact the PCI Special Interest Group office to obtain the latest revision of this checklistQuestions regarding the ths document or membership in the PCI Special Interest Group may be forwarded tPCI Special Interest Group5440 SW Westgate Drive #217Portland, OR 97221Phone: 503-291-2569Fax: 503-297-1090 DISCLAIMERThis document is provided "as is" with no warranties whatsoever, including any warranty of merchantability, noninfringement, fitness for any particular Purpose, or any warranty otherwise arising out of any proposal, specification, or sample. The PCI SIG disclaims all liability for infringement of proprietary rights, relating to use of information in this specification. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted herein.
标签： Architecture ExpressTM PCI
上传时间： 2013-11-03
上传用户：gy592333
PCI ExpressTM is the third generation of PCI (PeripheralComponent Interconnect) technology used to connect I/Operhipheral devices in computer systems. It is intended asa general Purpose I/O device interconnect that meets theneeds of a wide variety of computing platforms such asdesktop, mobile, server and communications. It alsospecifies the electrical and mechanical attributes of thebackplane, connectors and removable cards in thesesystems.
上传时间： 2013-11-17
上传用户：squershop
