Phase
共 296 篇文章
Phase 相关的电子技术资料，包括技术文档、应用笔记、电路设计、代码示例等，共 296 篇文章，持续更新中。
模拟cmos集成电路设计(design of analog
<P>模拟集成电路的设计与其说是一门技术，还不如说是一门艺术。它比数字集成电路设计需要更严格的分析和更丰富的直觉。严谨坚实的理论无疑是严格分析能力的基石，而设计者的实践经验无疑是诞生丰富直觉的源泉。这也正足初学者对学习模拟集成电路设计感到困惑并难以驾驭的根本原因。.<BR>美国加州大学洛杉机分校(UCLA)Razavi教授凭借着他在美国多所著名大学执教多年的丰富教学经验和在世界知名顶级公司(AT&
XAPP854-数字锁相环(DPLL)参考设计
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Many applications require a clock signal to be synchronous, phase-locked, or derived fromanother signal, such as a data signal or another clock. This type of clock circuit is important in
寄存器和环路滤波器的设计
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The MAX2870 ultra-wideband phase-locked loop (PLL) and voltagecontrol oscillator (VCO) can operate in both integer-N and fractional-Nmodes, similar to the Analog Devices ADF4350 wideband synthe
digital phase_division Verilog
digital phase_division Verilog
ML Estimation of frequency, phase, and amplitude of a sinusoid from discrete time samples MLEsim.m
ML Estimation of frequency, phase, and amplitude of a sinusoid from discrete time samples
MLEsim.m
Enhanced version of the Serial Peripheral Interface available on Motorola s MC68HC11 family of CPUs.
Enhanced version of the Serial Peripheral Interface available on Motorola s MC68HC11 family of CPUs.Enhancements include a wider supported operating frequency range, 4deep read and write fifos, and pr
This file is used to develop Phase locked loop.
This file is used to develop Phase locked loop.
Digital cellular telecommunications system (Phase 2+) AT command set for GSM Mobile Equipment (ME)
Digital cellular telecommunications system (Phase 2+)
AT command set for GSM Mobile Equipment (ME)
(GSM 07.07 version 7.4.0 Release 1998)
AD9859芯片资料
FEATURES<BR>400 MSPS internal clock speed<BR>Integrated 10-bit DAC<BR>32-bit tuning word<BR>Phase noise ≤ –120 dBc/Hz @ 1 kHz offset (DAC output)<BR>Excellent dynamic performance<BR>>75 dB SFDR @ 1
CD4046 phase-locked loop induction heating power supply in the application of induction heating
CD4046 phase-locked loop induction heating power supply in the application of induction heating
GPRS(General Packet Radio Service)是通用分组无线业务的简称。GPRS是GSM Phase2.1规范实现的内容之一
GPRS(General Packet Radio Service)是通用分组无线业务的简称。GPRS是GSM Phase2.1规范实现的内容之一，能提供比现有GSM网9.6kbit/s更高的数据率。GPRS采用与GSM 相同的频段、频带宽度、突发结构、无线调制标准、跳频规则以及相同的TDMA帧结构。因此，在GSM系统的基础上构建GPRS系统时，GSM系统中的绝大部分部件都不需要作硬件改动，只需作
XAPP806 -决定DDR反馈时钟的最佳DCM相移
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This application note describes how to build a system that can be used for determining theoptimal phase shift for a Double Data Rate (DDR) memory feedback clock. In this system, theDDR memory i
在DAB系统中的频率同步
在DAB系统中的频率同步，载频同步，参考一下Carrier frequency offset estimation of DAB receiver based on phase reference symbol
matlab simulink model for three phase inverter
matlab simulink model for three phase inverter
Three-phase diode rectifier 使用SIMULINK MATLAB仿真
Three-phase diode rectifier 使用SIMULINK MATLAB仿真
DDR SDRAM控制器的VHDL源代码
DDR SDRAM控制器的VHDL源代码，含详细设计文档。
The DDR, DCM, and SelectI/O™ features in the Virtex™ -II architecture make it the perfect
choice for implementing a controller of a Double Data Rate (DDR) SDR
This paper studies the problem of tracking a ballistic object in the reentry phase by processing ra
This paper studies the problem of tracking a ballistic object in
the reentry phase by processing radar measurements. A suitable
(highly nonlinear) model of target motion is developed and the
theore
Show work of ODE45 function. As the example use lorenz equation. Example show ensemble Puankare and
Show work of ODE45 function. As the example use lorenz equation. Example show ensemble Puankare and phase picture
计算全息close all clc clear A=zeros(64) A(15:20,20:40)=1 A(15:50,20:25)=1 A(45:50,20:40)=1 A(30:34,
计算全息close all clc clear
A=zeros(64)
A(15:20,20:40)=1 A(15:50,20:25)=1
A(45:50,20:40)=1 A(30:34,20:35)=1
％ ppp=exp(rand(64)*pi*2*i) A=A.*ppp
％ Author s email: zjliu2001@163.com
figure imshow(
This mfile illustrates a simple two path Rayleigh multipath fading channel This mfile inputs an unm
This mfile illustrates a simple two path Rayleigh multipath fading channel
This mfile inputs an unmodulated sinewave through a simple Rayleigh two path fading channel and shows the output with phase,