The AT89C52 is a low-POwer, high-performance CMOS 8-bit microcomputer with 8Kbytes of Flash programmable and erasable read only memory (PEROM). The deviceis manufactured using Atmel’s high-density nonvolatile memory technology and iscompatible with the industry-standard 80C51 and 80C52 instruction set and pinout.The on-chip Flash allows the program memory to be reprogrammed in-system or by aconventional nonvolatile memory programmer. By combining a versatile 8-bit CPUwith Flash on a monolithic chip, the Atmel AT89C52 is a POwerful microcomputerwhich provides a highly-flexible and cost-effective solution to many embedded controlapplications.
上传时间： 2013-11-10
上传用户：1427796291
中文版详情浏览：http://www.elecfans.com/emb/fpga/20130715324029.html Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications. The UltraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the UltraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation. Some of the UltraScale architecture breakthroughs include: • Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50% • Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability • Potential timing-closure problems and interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization • 3D IC integration makes it possible to build larger devices one process generation ahead of the current industr y standard • Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bandwidth is available within even smaller system POwer budgets • Greatly enhanced DSP and packet handling The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.
标签： UltraScale Xilinx 架构
上传时间： 2013-11-13
上传用户：瓦力瓦力hong
As businesses and consumers expect more fromportable electronics, the FPGA industry has beencompelled to re-think how it serves these low-POwer,cost-sensitive markets. Application classes like
上传时间： 2013-11-10
上传用户：XLHrest
This white paper discusses how market trends, the need for increased productivity, and new legislation have accelerated the use of safety systems in industrial machinery. This TÜV-qualified FPGA design methodology is changing the paradigms of safety designs and will greatly reduce development effort, system complexity, and time to market. This allows FPGA users to design their own customized safety controllers and provides a significant competitive advantage over traditional microcontroller or ASIC-based designs. Introduction The basic motivation of deploying functional safety systems is to ensure safe operation as well as safe behavior in cases of failure. Examples of functional safety systems include train brakes, proximity sensors for hazardous areas around machines such as fast-moving robots, and distributed control systems in process automation equipment such as those used in petrochemical plants. The International Electrotechnical Commission’s standard, IEC 61508: “Functional safety of electrical/electronic/programmable electronic safety-related systems,” is understood as the standard for designing safety systems for electrical, electronic, and programmable electronic (E/E/PE) equipment. This standard was developed in the mid-1980s and has been revised several times to cover the technical advances in various industries. In addition, derivative standards have been developed for specific markets and applications that prescribe the particular requirements on functional safety systems in these industry applications. Example applications include process automation (IEC 61511), machine automation (IEC 62061), transportation (railway EN 50128), medical (IEC 62304), automotive (ISO 26262), POwer generation, distribution, and transportation. 图Figure 1. Local Safety System
上传时间： 2013-11-05
上传用户：维子哥哥
Abstract: There are many things to consider when designing a POwer supply for a field-programmablegate array (FPGA). These include (but are not limited to) the high number of voltage rails, and thediffering requirements for both sequencing/tracking and the voltage ripple limits. This application noteexplains these and other POwer-supply considerations that an engineer must think through whendesigning a POwer supply for an FPGA.
上传时间： 2013-11-10
上传用户：iswlkje
Abstract: This reference design explains how to POwer the Xilinx Zynq Extensible Processing Platform (EPP) and peripheral ICs using
上传时间： 2014-01-21
上传用户：haohao
Xilinx FPGAs require at least two POwer supplies: VCCINTfor core circuitry and VCCO for I/O interface. For the latestXilinx FPGAs, including Virtex-II Pro, Virtex-II and Spartan-3, a third auxiliary supply, VCCAUX may be needed. Inmost cases, VCCAUX can share a POwer supply with VCCO.The core voltages, VCCINT, for most Xilinx FPGAs, rangefrom 1.2V to 2.5V. Some mature products have 3V, 3.3Vor 5V core voltages. Table 1 shows the core voltagerequirement for most of the FPGA device families. TypicalI/O voltages (VCCO) vary from 1.2V to 3.3V. The auxiliaryvoltage VCCAUX is 2.5V for Virtex-II Pro and Spartan-3, andis 3.3V for Virtex-II.
上传时间： 2013-10-22
上传用户：liu999666
Xilinx Next Generation 28 nm FPGA Technology Overview Xilinx has chosen 28 nm high-κ metal gate (HKMG) highperformance,low-POwer process technology and combined it with a new unified ASMBL™ architecture to create a new generation of FPGAs that offer lower POwer and higher performance. These devices enable unprecedented levels of integration and bandwidth and provide system architects and designers a fully programmable alternative to ASSPs and ASICs.
上传时间： 2014-12-28
上传用户：zhang97080564
WP369可扩展式处理平台-各种嵌入式系统的理想解决方案 ：Delivering unrivaled levels of system performance,flexibility, scalability, and integration to developers,Xilinx's architecture for a new Extensible Processing Platform is optimized for system POwer, cost, and size. Based on ARM's dual-core Cortex™-A9 MPCore processors and Xilinx’s 28 nm programmable logic,the Extensible Processing Platform takes a processor-centric approach by defining a comprehensive processor system implemented with standard design methods. This approach provides Software Developers a familiar programming environment within an optimized, full featured,POwerful, yet low-cost, low-POwer processing platform.
上传时间： 2013-10-22
上传用户：685
选择映射法（SLM）和概率类算法都可以降低OFDM （Orthogonal Frequency Division Multiplexing）系统的PAPR（Peak to Average POwer Ratio），传统SLM算法自身较为复杂，但由于其优良的性能，弃之可惜。研究表明，SLM算法和限幅类算法在性能上具有一定的互补性。任何一个算法未必能达到抑制PAPR的理想效果，在深入研究了两个算法的基础上，将其优点联合起来，以达到降低OFDM系统PAPR的目的。最后对联合改进算法进行了分析与仿真，并验证了联合改进算法的有效性和可行性
上传时间： 2013-11-22
上传用户：xinhaoshan2016
