源码文件
[Design] Version=1.0 HierarchyMode=0 ChannelRoomNamingStyle=0 OutputPath=Out ChannelDesignatorFormatString=$Component_$RoomNa…
汇集 POWER+LOGIC 相关的电路原理图、PCB工程文件、单片机/FPGA源代码、数据手册与应用设计方案。
[Design] Version=1.0 HierarchyMode=0 ChannelRoomNamingStyle=0 OutputPath=Out ChannelDesignatorFormatString=$Component_$RoomNa…
[Preview] LargeImageOriginalSize=662000 LargeImageWidth=500 LargeImageHeight=331 LargeImage=78DAEDDDEB6F5CE95DC0F1E74FE91F8084…
[DISPLAYS] BEGIN DISPLAY LAST SESSION ANALYSIS TRANSIENT_ANALYSIS SYMBOL ALWAYS TRACECOLORSCHEME NORMAL BEGIN ANAPLOT 1 ACTI…