iic总线控制器VHDL实现 -- VHDL Source Files: i2c.vhd -- top level file i2c_control.vhd -- control function for the I2C master/slave shift.vhd -- shift register uc_interface.vhd -- uC interface function for an 8-bit 68000-like uC upcnt4.vhd -- 4-bit up counter i2c_timesim.vhd -- post-route I2C simulation netlist
标签： VHDL c_control vhd control
上传时间： 2016-10-30
上传用户：woshiayin
设计一个鼠标程序，在按下Ctrl键的同时按下鼠标左键，在窗口中拖动鼠标，可以画出一个圆；在按下Shift键的同时按下鼠标左键，在窗口中拖动鼠标，画出一个矩形。
上传时间： 2013-12-22
上传用户：jiahao131
* The keyboard is assumed to be a matrix having 4 rows by 6 columns. However, this code works for any * matrix arrangements up to an 8 x 8 matrix. By using from one to three of the column inputs, the driver * can support "SHIFT" keys. These keys are: SHIFT1, SHIFT2 and SHIFT3.
标签： keyboard However assumed columns
上传时间： 2016-11-14
上传用户：ardager
51单片机C语言多种点阵屏驱动程序（开发软件为keil C ---8字点阵屏左移程序，64_16点阵屏驱动程序，上移显示程序，左移显示程序）51 monolithic integrated circuit C language many kinds of lattice screen driver (develops the software is keil C ---8 character lattice screen left shift procedure, the 64_16 lattice screen driver, uppers shift the display sequence, the left shift display sequence
上传时间： 2014-01-04
上传用户：Ants
PRINCIPLE: The UVE algorithm detects and eliminates from a PLS model (including from 1 to A components) those variables that do not carry any relevant information to model Y. The criterion used to trace the un-informative variables is the reliability of the regression coefficients: c_j=mean(b_j)/std(b_j), obtained by jackknifing. The cutoff level, below which c_j is considered to be too small, indicating that the variable j should be removed, is estimated using a matrix of random variables.The predictive power of PLS models built on the retained variables only is evaluated over all 1-a dimensions =(yielding RMSECVnew).
标签： from eliminates PRINCIPLE algorithm
上传时间： 2016-11-27
上传用户：凌云御清风
The VGA example generates a 320x240 diffusion-limited-aggregation (DLA) on Altera DE2 board. A DLA is a clump formed by sticky particles adhering to an existing structure. In this design, we start with one pixel at the center of the screen and allow a random walker to bounce around the screen until it hits the pixel at the center. It then sticks and a new walker is started randomly at one of the 4 corners of the screen. The random number generators for x and y steps are XOR feedback shift registers (see also Hamblen, Appendix A). The VGA driver, PLL, and reset controller from the DE2 CDROM are necessary to compile this example. Note that you must push KEY0 to start the state machine.
标签： diffusion-limited-aggregation DLA generates 320x240
上传时间： 2014-01-16
上传用户：225588
M16C/6S 群是采用64 管脚的塑模LQFP 封装的单片机。该群将电力线通信调制解调器内核（利用了Yitran Communications Ltd公司开发的IT800PLC调制解调器技术）和模拟前端进行了单芯片化。M16C/60系列CPU内 核实现了高级别的编码效率和高速运算处理，而且，内置的IT800调制解调器内核还采用了Yitran公司的DCSK （Differential Code Shift Keying）扩频调制方式的专利技术，可在已有的电气配线上实现速度最大为7.5kbps的高 可靠性的通信。M16C/6S符合国际标准（FCC part 15, ARIB and CENELEC bands），最适合用于AMR（Automatic Meter Reading）或家庭自动化控制系统等各种窄带的应用程序。
标签： Communications Yitran LQFP 800
上传时间： 2014-08-08
上传用户：xaijhqx
DDR SDRAM控制器的VHDL源代码，含详细设计文档。 The DDR, DCM, and SelectI/O™ features in the Virtex™ -II architecture make it the perfect choice for implementing a controller of a Double Data Rate (DDR) SDRAM. The Digital Clock Manager (DCM) provides the required Delay Locked Loop (DLL), Digital Phase Shift (DPS), and Digital Frequency Synthesis (DFS) functions. This application note describes a controller design for a 16-bit DDR SDRAM. The application note and reference design are enhanced versions of XAPP200 targeted to the Virtex-II series of FPGAs. At a clock rate of 133 MHz, 16-bit data changes at both clock edges. The reference design is fully synthesizable and achieves 133 MHz performance with automatic place and route tools.
上传时间： 2014-11-01
上传用户：l254587896
neural network utility is a Neural Networks library for the C++ Programmer. It is entirely object oriented and focuses on reducing tedious and confusing problems of programming neural networks. By this I mean that network layers are easily defined. An entire multi-layer network can be created in a few lines, and trained with two functions. Layers can be connected to one another easily and painlessly.
标签： Programmer Networks entirely network
上传时间： 2013-12-24
上传用户：liuchee
GPS 接收程序 DEMO。 HsGpsDll Library 1.1 A GPS Control/Component for C/C++ HsGpsDll is a Windows Dynamic Link Library which provides access to any NMEA-183 compliant GPS receiver via a serial communications port. HsGpsDll is designed for use from Visual C, Visual Basic or other languages, capable of calling DLL functions. HsGpsDll allows a user application to read from a GPS device the current GPS position fix, velocity over ground (speed in kilometers per hour), plus number of of sattelites in view, current altitude (against mean sea level) and UTC date and time
标签： HsGpsDll GPS Component Control
上传时间： 2014-07-17
上传用户：thuyenvinh
