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https://www.eeworm.com/dl/663/226442.html
VHDL/FPGA/Verilog
This leon3 design is tailored to the Altera NiosII Startix2 Development board, with 16-bit DDR SDR
This leon3 design is tailored to the Altera NiosII Startix2
Development board, with 16-bit DDR SDRAM and 2 Mbyte of SSRAM.
As of this time, the DDR interface only works up to 120 MHz.
At 130, DDR data can be read but not written.
NOTE: the test bench cannot be simulated with ...
https://www.eeworm.com/dl/895114.html
技术资料
基于嵌入式的高速数据采集系统
在遥测系统中，针对传统存储系统硬盘的功耗高、发热高、噪声大、访问速度低的问题，设计了以 FPGA 为主控单元，以 LVDS 为图像数据传输和读取的接口。以图像存储、图像传输、长线读数和实时监测为主要功能模块。以 FLASH 为存储单元，合理地选择了存储模块的工作模式，根据可靠性和模块化的设计原则， ...