Log Shifter Gate Level Design using Verilog(IC design Lab) and Lab Note
Level+Sets 技术资料
汇集 Level+Sets 相关的电路原理图、PCB工程文件、单片机/FPGA源代码、数据手册与应用设计方案。
This book provides a complete intermediate-level discussion of microcontroller programming using the C programming language. It co…
本教程针对HLSL (High Level Shading Language )初学者,从应用的角度对HLSL、顶点着色器、像素着色器和Effect 效果框架进行了介绍,教程中去掉了对HLSL 语法等一些细节内容的讨论,力求帮助读者尽可能快地理解HLSL 编程…
TTCAN 是基于CAN 的时间触发的高层协议,具有确定性行为,因而适用于安全相关的场合。本文首先从参照时间、基本周期、系统信息阵、网络时间单元和全局时间五个方面对TTCAN 协议进行分析,其后讲解了
There is a shared object – int array[] between Write and Read. Write sets the array, Read gets the a
There is a shared object – int array[] between Write and Read. Write sets the array, Read gets the array and sorts ascending. Writ…
This Document provides the High Level Design specification for the Bootloader development and librar
This Document provides the High Level Design specification for the Bootloader development and library porting for ADSP-BF533 based…
Implicit and Non-parametric Shape Reconstruction from Unorganized Data using a Variational Level Set
Implicit and Non-parametric Shape Reconstruction from Unorganized Data using a Variational Level Set Method
一篇关于多level set 分割的经典论文,作者是tony chan,里面加有注释
05 finland PhD User-Level Reliability and Quality Monitoring in Satellite-Based Personal Navigation.
资料->【E】光盘论文->【E1】斯坦福博士论文->05 finland PhD User-Level Reliability and Quality Monitoring in Satellite-Based Personal Navigation.pdf
This example sets up the PLL in x10/2 mode, divides SYSCLKOUT by six to reach a 25Mhz HSPCLK (assumi
This example sets up the PLL in x10/2 mode, divides SYSCLKOUT by six to reach a 25Mhz HSPCLK (assuming a 30Mhz XCLKIN). The clock …