INduced
共 10 篇文章
INduced 相关的电子技术资料，包括技术文档、应用笔记、电路设计、代码示例等，共 10 篇文章，持续更新中。
期刊论文：The Hyperbolic Geometry of Illumination-Induced Chromaticity Chan
·The Hyperbolic Geometry of Illumination-Induced Chromaticity Changes [cvpr07]
直流电动机测速装置
<p>本系统采用电动机电枢供电回路串接采样电阻的方式来实现对小型直流有刷电动机的转速测量。该系统主要由二阶低通滤波电路,小信号放大电路、单片机测量显示电路、开关稳压电源电路等组成。同时自制电机测速装置,用高频磁环作为载体,用线圈绕制磁环,利用电磁感应原理检测电机运行时的漏磁,将变化的磁场信号转化为磁环上的感应电流。用信号处理单元电路将微弱电信号转化为脉冲信号,送由单片机检测,从而达到准确测量电机的
Smart+Antennas
Smart antennas involve processing of signals induced on an array of sensors such as<br />
antennas, microphones, and hydrophones. They have applications in the areas of radar,<br />
sonar, medical ima
Core+and+Metro+Networks
It is commonly accepted today that optical fiber communications have revolutionized<br />
telecommunications. Indeed, dramatic changes have been induced in the way we interact<br />
with our relatives
Analysis+of+Device-to-Device+Communications
Device-to-device(D2D) communications are now considered as an integral part of future 5G networks<br />
which will enable direct communication between user equipment (UE) without unnecessary routing v
The algorithm ID3 (Quinlan) uses the method top-down induction of decision trees. Given a set of cla
The algorithm ID3 (Quinlan) uses the method top-down induction of decision trees. Given a set of classified examples a decision tree is induced, biased by the information gain measure, which heuristic
频繁INduced子树聚类算法FREQT
频繁INduced子树聚类算法FREQT，很好的
Programs to induce a naive possibilistic classifier (a possibilistic analog of the naive Bayes class
Programs to induce a naive possibilistic classifier (a possibilistic analog of the naive Bayes classifier) and to classify new data with an induced naive possibilistic classifier.
高速电路传输线效应分析与处理
随着系统设计复杂性和集成度的大规模提高，电子系统设计师们正在从事100MHZ以上的电路设计，总线的工作频率也已经达到或者超过50MHZ，有一大部分甚至超过100MHZ。目前约80% 的设计的时钟频率超过50MHz，将近50% 以上的设计主频超过120MHz，有20%甚至超过500M。<BR>当系统工作在50MHz时，将产生传输线效应和信号的完整性问题；而当系统时钟达到120MHz时，除非使用高速电
高速电路传输线效应分析与处理
随着系统设计复杂性和集成度的大规模提高，电子系统设计师们正在从事100MHZ以上的电路设计，总线的工作频率也已经达到或者超过50MHZ，有一大部分甚至超过100MHZ。目前约80% 的设计的时钟频率超过50MHz，将近50% 以上的设计主频超过120MHz，有20%甚至超过500M。<BR>当系统工作在50MHz时，将产生传输线效应和信号的完整性问题；而当系统时钟达到120MHz时，除非使用高速电