基于FPGA的I2C总线模拟
基于FPGA的I2C总线模拟,采用verilog HDL语言编写。- Based on the FPGA I2C main line simulation, uses verilog the HDL language compilation....
基于FPGA的I2C总线模拟,采用verilog HDL语言编写。- Based on the FPGA I2C main line simulation, uses verilog the HDL language compilation....
USB接口的VHDL源码,支持Verilog HDL程序...
CAN总线IPCORE,采用Verilog HDL语言实现。...
十六位的除法器,采用verilog hdl...
华为Verilog HDL入门的一些资料...