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Harvard 的查询结果
电子书籍 Harvard教授Gray所写的统计信号处理
Harvard教授Gray所写的统计信号处理
单片机编程 几款单片机的原理介绍
几款单片机的原理介绍
主要单片机的介绍1. ATMEL公司的AVR单片机,是增强型RISC内载Flash的单片机,芯片上的Flash存储器附在用户的产品中,可随时编程,再编程,使用户的产品设计容易,更新换代方便.AVR单片机采用增强的RISC结构,使其具有高速处理能力,在一个时钟周期内可执行复杂的指令,每MHz可实现1MIPS的处理能力.AVR单片机工 ...
ARM LPC1850 Cortex-M3内核微控制器数据手册
The LPC1850/30/20/10 are ARM Cortex-M3 based microcontrollers for embeddedapplications. The ARM Cortex-M3 is a next generation core that offers systemenhancements such as low power consumption, enhanced debug features, and a highlevel of support block integration.The LPC1850/30/20/10 operate at CPU ...
ARM LPC4300系列ARM双核微控制器产品数据手册
The LPC4350/30/20/10 are ARM Cortex-M4 based microcontrollers for embeddedapplications. The ARM Cortex-M4 is a next generation core that offers systemenhancements such as low power consumption, enhanced debug features, and a highlevel of support block integration.The LPC4350/30/20/10 operate at CPU ...
DSP编程 The TMS320C54x, TMS320LC54x, and TMS320VC54x fixed-point, digital signal processor (DSP) families (
The TMS320C54x, TMS320LC54x, and TMS320VC54x fixed-point, digital signal processor (DSP) families
(hereafter referred to as the ’54x unless otherwise specified) are based on an advanced modified Harvard
architecture that has one program memory bus and three data memory buses. These processors also ...
书籍源码 The NCTUns network simulator and emulator is developed at NCTU, Taiwan. Its predecessor is the Harva
The NCTUns network simulator and emulator is developed at NCTU, Taiwan. Its predecessor is the Harvard network simulator (invented by Prof. S.Y. Wang in 1999).
By using a novel simulation methodology, it can do several tasks that traditional network simulators cannot easily do.
Windows CE pccard driver s3c2440.The S3C2440A offers outstanding features with its CPU core, a 16/32-bit ARM92
pccard driver s3c2440.The S3C2440A offers outstanding features with its CPU core, a 16/32-bit ARM920T RISC processor designed by
Advanced RISC Machines, Ltd. The ARM920T implements MMU, AMBA BUS, and Harvard cache architecture
with separate 16KB instruction and 16KB data caches, each with an 8-word ...