Functional+Safety 源代码

汇集 Functional+Safety 相关的电路原理图、PCB工程文件、单片机/FPGA源代码、数据手册与应用设计方案。

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源码文件

// Shared.h: interface for the Shared Define. // ////////////////////////////////////////////////////////////////////// #ifnd…

源码文件

Compiled with CC = cl2 /nologo INCLUDE = E:\MICROS~1.NET\VC7\ATLMFC\INCLUDE;E:\MICROS~1.NET\VC7\INCLUDE; 0.cpp 2-1.cpp 2…

源码文件

/****************************************************************************** * * LOGIC CORE: SDR SDRAM Controller -…

源码文件

#include #include #include "carray.h" #include "print.h" using namespace std; int main() { carray a; for(unsig…

源码文件

--IP Functional Simulation Model --VERSION_BEGIN 4.1 cbx_mgl 2004:06:17:17:30:06:SJ cbx_simgen 2004:07:08:11:13:28:SJ VERSION_EN…

源码文件

1) To give list with local procedure vars and global vars and allow user to change their name. 2) DFM Editor. Allow editing (chan…

源码文件

--IP Functional Simulation Model --VERSION_BEGIN 7.1SP1 cbx_mgl 2007:06:11:08:05:04:SJ cbx_simgen 2007:03:19:10:39:32:SJ VERSION…

源码文件

Started process "View HDL Functional Model". ERROR:DesignEntry:30 - Instance "XLXI_3" referencing symbol "VSP2232" is out of d…

源码文件

// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/INV.v,v 1.5 2005/03/14 22:32:53 yanx Exp $ ////////…

源码文件

// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/XORCY.v,v 1.5 2005/03/14 22:32:58 yanx Exp $ //////…