源码文件
Release 6.3i Map G.35 Xilinx Mapping Report File for Design 'bit_add' Design Information ------------------ Command Line : E:/X…
FPGA+Design 源代码
汇集 FPGA+Design 相关的电路原理图、PCB工程文件、单片机/FPGA源代码、数据手册与应用设计方案。
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源码文件
//-------------------------------------------------------------------------------------------------- // Design : nova // Author…
源码文件
# Design Explorer: Shortcut to "D:\My_Designs\Samples_63\SN7485\SN7485.aws" design added.
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# Design Explorer: Shortcut to "D:\My_Designs\Samples_63\memory_example\memory_example.aws" design added.
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# Design Explorer: Shortcut to "D:\My_Designs\Samples_63\Generator\generator.aws" design added.
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**********************************************************************************************************************************…
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(ExpressProject "Design1" (ProjectVersion "19981106") (ProjectType "PCB") (Folder "Design Resources" (Folder "Librar…
源码文件
function y=design(x) % DESIGN % DESIGN(x) creates a matrix of 1 and 0 corresponding to x % y: Rows(x) x Max(x) i=1:1:rows(x…
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DE2_Tv ------ This design converts DVD video into a format suitable for display on a CRT/LCD monitor. A DVD video source, such…
源码文件
Release 7.1.01i Map H.39 Xilinx Mapping Report File for Design 'electronic_organ' Design Information ------------------ Command L…