12864液晶显示
标签： 12864 characters pictures Display
上传时间： 2013-11-12
上传用户：懒龙1988
软件介绍与下载事项： .Zah287 { Display:none; } _)(^$RFSW#$%T
上传时间： 2013-10-28
上传用户：fnggknj
Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the developmentof designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, Display, post, or transmit theDocumentation in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise,without the prior written consent of Xilinx. Xilinx expressly disclaims any liability arising out of your use of the Documentation. Xilinx reservesthe right, at its sole discretion, to change the Documentation without notice at any time. Xilinx assumes no obligation to correct any errorscontained in the Documentation, or to advise you of any corrections or updates. Xilinx expressly disclaims any liability in connection withtechnical support or assistance that may be provided to you in connection with the Information.
上传时间： 2013-11-11
上传用户：zwei41
According to CIBC World Markets, Equity Research, theFlat Panel Display (FPD) industry has achieved sufficientcritical mass for its growth to explode. Thus, it can nowattract the right blend of capital investments and R&Dresources to drive technical innovation toward continuousimprovement in view quality, manufacturing efficiency,and system integration. These in turn are sustainingconsumer interest, penetration, revenue growth, and thepotential for increasing long-term profitability for industryparticipants. CIBC believes that three essential conditionsare now converging to drive the market forward
上传时间： 2015-01-02
上传用户：小枫残月
Consumer Display applications commonly use high-speed LVDS interfaces to transfer videodata. Spread-spectrum clocking can be used to address electromagnetic compatibility (EMC)issues within these consumer devices. This application note uses Spartan®-6 FPGAs togenerate spread-spectrum clocks using the DCM_CLKGEN primitive.
上传时间： 2013-11-01
上传用户：hjkhjk
This application note covers the design considerations of a system using the performance features of the LogiCORE™ IP Advanced eXtensible Interface (AXI) Interconnect core. The design focuses on high system throughput through the AXI Interconnect core with F MAX and area optimizations in certain portions of the design. The design uses five AXI video direct memory access (VDMA) engines to simultaneously move 10 streams (five transmit video streams and five receive video streams), each in 1920 x 1080p format, 60 Hz refresh rate, and up to 32 data bits per pixel. Each VDMA is driven from a video test pattern generator (TPG) with a video timing controller (VTC) block to set up the necessary video timing signals. Data read by each AXI VDMA is sent to a common on-screen Display (OSD) core capable of multiplexing or overlaying multiple video streams to a single output video stream. The output of the OSD core drives the DVI video Display interface on the board. Performance monitor blocks are added to capture performance data. All 10 video streams moved by the AXI VDMA blocks are buffered through a shared DDR3 SDRAM memory and are controlled by a MicroBlaze™ processor. The reference system is targeted for the Virtex-6 XC6VLX240TFF1156-1 FPGA on the Xilinx® ML605 Rev D evaluation board
上传时间： 2013-11-23
上传用户：shen_dafa
Xilinx is disclosing this user guide, manual, release note, and/or specification (the “Documentation”) to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, Display, post, or transmit the Documentation in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise, without the prior written consent of Xilinx. Xilinx expressly disclaims any liability arising out of your use of the Documentation. Xilinx reserves the right, at its sole discretion, to change the Documentation without notice at any time. Xilinx assumes no obligation to correct any errors contained in the Documentation, or to advise you of any corrections or updates. Xilinx expressly disclaims any liability in connection with technical support or assistance that may be provided to you in connection with the Information.
标签： CPLD
上传时间： 2014-12-05
上传用户：qazxsw
§1、安装： SPB15.2 CD1～3，安装1、2，第3为库，不安装 License安装： 设置环境变量lm_license_file D:\Cadence\license.dat 修改license中SERVER yyh ANY 5280为SERVER zeng ANY 5280 §2、用Design Entry CIS(Capture)设计原理图 进入Design Entry CIS Studio 设置操作环境\Options\Preferencses: 颜色：colors/Print 格子：Grid Display 杂项：Miscellaneous .........常取默认值
上传时间： 2014-01-25
上传用户：wangcehnglin
本文利用Verilog HDL 语言自顶向下的设计方法设计多功能数字钟，突出了其作为硬件描述语言的良好的可读性、可移植性和易理解等优点，并通过Altera QuartusⅡ 4.1 和ModelSim SE 6.0 完成综合、仿真。此程序通过下载到FPGA 芯片后，可应用于实际的数字钟显示中。 关键词：Verilog HDL；硬件描述语言；FPGA Abstract: In this paper, the process of designing multifunctional digital clock by the Verilog HDL top-down design method is presented, which has shown the readability, portability and easily understanding of Verilog HDL as a hard description language. Circuit synthesis and simulation are performed by Altera QuartusⅡ 4.1 and ModelSim SE 6.0. The program can be used in the truly digital clock Display by downloading to the FPGA chip. Keywords: Verilog HDL；hardware description language；FPGA
上传时间： 2013-11-10
上传用户：hz07104032
Displaying a large bitmap file on a dialog box, in its original size, is quite difficult in the VC++ environment. However, it is possible to Display a large bitmap to a predefined area of the dialog by using the StretchBlt( ) function.The major disadvantage of this is that the clarity of the image will be lost. Check out this article for Displaying large bitmaps into the desired area of your dialog box in its original size with a scrolling technique used to show the entire bitmap. 滚动显示位图 在VC++环境下，在一个对话框中显示一个原始尺寸的大小的位图文件相当是困难的。然而,通过使用 StretchBlt()函数一个给定的区域显示一个大的位图是可能的。主要的缺点是图像将会失真。看了这篇通过卷动技术显示整个位图技术的文章，你将能够以它的原始尺寸在给定对话框的区域内显示一个大位图。 来源: http://www.codeguru.com/bitmap/ScrollBitmap.html
标签： Displaying difficult original bitmap
上传时间： 2014-01-05
上传用户：yiwen213
