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查看全部 1,612 份 →一个简单的Modular Design设计,源代码
一个简单的Modular Design设计,源代码，分别用Verilog和VHDL两种语言描述，本设计顶层模块由3个子模块组成.
2016-06-28
50
This documents is about RF Filter design using Coupled Co-axial Resonators.
This documents is about RF Filter design using Coupled Co-axial Resonators.
2017-07-11
64
Simulation and Synthesis Techniques for Asynchronous FIFO Design with Asynchronous Pointer Comparis
Simulation and Synthesis Techniques for Asynchronous FIFO Design with Asynchronous Pointer Comparisons
2017-07-19
109
This book used in HDL language, the name is Advanced FPGA Design.
This book used in HDL language, the name is Advanced FPGA Design.
2014-01-31
56